ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 160

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.5.2.64 Data Memory Subsystem Configuration 1 MSR (DM_CONFIG1_MSR)
MSR Address
Type
Reset Value
160
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:48
47:32
31:27
26:25
23:22
Bits
24
21
RSVD
Name
RSVD
APFLOCK
RSVD
APFMODE
APFENA
RSVD
PFXLOCKENA
00001801h
R/W
00000000_00000000h
33234C
RSVD
RSVD
Description
Reserved.
Auto-Prefetch Lock. Bit mask of ways that cannot be allocated or replaced on an auto-
prefetch issued for a cache miss due to an instruction that is not using the restricted
cache prefix. Automatic prefetches that result from restricted cache prefix instructions
use the PFXLOCK field (bits [15:0]) for way masking. (Default = 0)
Reserved.
Auto-Prefetch Mode. When auto-prefetching is enabled via the APFENA bit (bit 24),
APFMODE determines how the prefetches are issued as follows:
00: Even Only. An auto-prefetch is issued for the odd cache line when a fill is issued for
01: Even/Odd. Auto-prefetches are issued for an odd cache line when an even fill is
1x: Increment. Auto-prefetches are issued for the next cache line (auto-prefetch line = fill
Auto-Prefetch Enable. Allows DM to perform automatic prefetch operations based on
cache fills as specified by the APFMODE field (bits [26:25]).
0: Disable.
1: Enable.
Reserved.
Prefetch Prefix Instructions Lock Enable. When this bit is enabled, the LSLOCK field
in DM_CONFIG0 (MSR 00001800h[31:16]) determines which ways are available for
replacement for all processor memory references except prefetch instructions.
0: Disable the restricted cache feature. (Default)
1: Enable the restricted cache feature (PFXLOCK field, bits [15:0]).
an even cache line, but no auto-prefetch is issued for a fill on an odd cache line. For
example, when a fill request is issued for address 0h, a prefetch will be issued for
address 20h. (Default)
issued, and for even cache lines when an odd fill is issued. (i.e the auto-prefetch
address is the toggle of fill address A[5]). Using this mode effectively increases the
DM logical cache line size to 64 bytes for fills. Line replacements and snoop evictions
are still done using a 32-byte line size.
line + 1) when a fill is issued, except for the last cache line in a 4K page (fill address
bits [11:5] = 1111111b).
DM_CONFIG1_MSR Bit Descriptions
DM_CONFIG1_MSR Register Map
ARRAYDIS
AMD Geode™ LX Processors Data Book
9
APFLOCK
PFXLOCK
8
CPU Core Register Descriptions
7
6
5
4
3
2
1
0