ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 414

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

414
13:8
Bit
7:6
5:3
2:0
15
14
Name
FPC
IUV
DIV
FMTBO
FMT
PID
33234C
GLD_MSR_CONFIG Bit Descriptions (Continued)
Description
Simultaneous Flat Panel (or VOP) and CRT. Primary display is flat panel. Setting this
bit activates the CRT DAC interface to allow simultaneous display of both panel and
CRT. Leaving this bit reset forces the CRT DAC signals to zero.
This bit is ignored if bits [5:3] of this register are set to 0 or 4.
Interchange UV. Interchange byte order of the U and V bytes (see bits [7:6]). This
applies only to DRGB mode (see bits [5:3]).
Clock Divider. GLIU clock divider to produce 14.3 MHz reference clock. Result must be
equal to or less than 14.3 MHz. GLIU clock speed/DIV = reference clock.
Format Byte Order. The lower 24 bits of the DRGB output bus byte order can be modi-
fied for any required interface. These bits, along with bit 14, are used to output the follow-
ing combinations of byte order. This applies only to DRGB mode.
000 = RGB / YUV (YC
001 = BGR / VUY (C
010 = BGR / VYU (C
011 = BRG / VUY (C
100 = RGB / YVU (YC
101 = BGR / VYU (C
110 = BGR / VUY (C
111 = BRG / VYU (C
VP Output Format Select. Video Processor module display outputs formatted for CRT
or flat panel. Resets to CRT; software must change if a different mode is required.
000: CRT.
001: Flat Panel.
010: Reserved.
011: Reserved.
100: CRT Debug mode.
101: Reserved.
110: VOP.
111: DRGB.
VP Priority Domain. Video Processor module assigned priority domain identifier.
r
r
r
r
r
r
C
YC
C
YC
C
YC
b
r
C
b
b
b
C
Y)
Y)
Y)
b
b
b
b
r
)
)
)
)
)
AMD Geode™ LX Processors Data Book
Video Processor Register Descriptions