ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 554

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.14.2.15 GLCP Debug Clock Control (GLCP_DBGCLKCTL)
MSR Address
Type
Reset Value
Note that after the mux to select the clock, a standard clock control gate exists. This register should never be changed from
one non-zero value to another. Always write this register to 0 when moving to an alternative debug clock.
554
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:49
46:44
43:36
35:32
31:26
23:16
12:10
9:1
Bit
48
47
25
24
15
14
13
0
Name
RSVD
DIV4
RSVD
MDIV
NDIV
PDIV
SWFLAGS
LOCK (RO)
HALFPIX
RSVD
BYPASS
PD
CAPEN
RSVD
RSVD
DOTRESET
4C000016h
R/W
00000000_00000002h
33234C
Description
Reserved. Write as read.
Divide by 4. When set, the PLL output is divided by 4 before clocking the logic. This bit
is intended for generating frequencies below the PLL spec limit of 15 MHz.
Reserved.
Input Clock Divisor. The DOTPLL M setting (resets to VGA timing).
Dot Clock PLL Divisor. The DOTPLL N setting (resets to VGA timing).
Post Scaler Divisor. The DOTPLL P setting (resets to VGA timing).
Software Flags. Unlike in the GLCP_SYS_RSTPLL register (MSR 4C000014h), these
bits are reset to 0 by a soft reset to the chip. These bits are otherwise read/writable by
software. They are not reset by a DOTRESET (bit 0 of this register).
Lock (Read Only). Lock signal from the DOTCLK PLL.
Half Pixel. The DC and VP receive a half-frequency Dot clock while the VOP logic
receives the normal frequency determined by the MDIV, NDIV, PDIV settings. This fea-
ture enables 8-bit VOP of SD data at 27 MHz VOP clock (pixel rate only 13.5 MHz).
Reserved. Write as read.
Dot PLL Bypass. This signal controls the bypass mode of the DOTCLK PLL. If this bit is
high, the DOTREF input clock directly drives the raw DOTCLK, bypassing the MDIV,
NDIV, and PDIV logic.
Power Down. This bit controls the power down mode of the DOTCLK PLL. It is active
high.
Capacitor Enable. The CAPEN signal to the DOTPLL enables the external capacitor for
loop filter.
Reserved.
Reserved. Read/writable bits not currently used.
DOT Clock Reset. The reset pin to the Dot clock time blocks. The Dot reset is held
active when CHIP_RESET (MSR 4C000014h[0]) is high, but this bit resets to 0. It is rec-
ommended that software set this bit when changing PLL settings and observe LOCK
before releasing this reset. Unlike the SYS_RSTPLL register, this bit is not required to be
set before the other bits in this register affect the PLL.
GLCP_DBGCLKCTL Register Map
GLCP_DOTPLL Bit Descriptions
RSVD
RSVD
GeodeLink™ Control Processor Register Descriptions
AMD Geode™ LX Processors Data Book
9
8
7
6
5
4
3
2
CLKSEL
1
0