ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 609

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Electrical Specifications
Note 1. Refer to Figure 7-8 "DDR Write Timing Measurement Points" on page 610 and Figure 7-9 "DDR Read Timing Mea-
Note 2. The SDCLKP and SDCLKN clocks are inversions of each other (differential clocking).
Note 3. These parameters guarantee device timing, but they may be tested to a looser value to allow for tester uncertain-
Note 4. t
Note 5. The DQ timing relative to DQS are on a per-byte basis only. DQ[7:0] and DQM[0] should be measured against
AMD Geode™ LX Processors Data Book
Symbol
(Note 1)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
CH
CL
SKEW1
DEL1
DQSCK
DEL2
RPRE
RPST
WPRE
WPST
DQSQs
DQSQh
VAL1
VAL2
surement Points" on page 611.
ties. Devices that meet the loosened tester values meet specs when correlated with lab measurements.
GLCP_DELAY_CONTROLS MSR. Typical tester results with clock and address loaded equally and no pro-
grammed delay for address are 0 ns for t
DQS[0], DQ[15:8] and DQM[1] should be measured against DQS[1], etc.
VAL2
Parameter
SDCLK[5:0]P, SDCLK[5:0]N period
SDCLK[5:0]P, SDCLK[5:0]N High time
SDCLK[5:0]P, SDCLK[5:0]N Low time
SDCLK[n]P to SDCLK[n]N skew (n=0..5)
SDCLK[5:1]P, SDCLK[5:0]N edge delay from
SDCLK[0]P
DQS[7:0] Input and output period
DQS[7:0] Input delay relative to SDCLK[5:0]
DQS[7:0] output edge delay from SDCLK[5:0]
DQS input preamble before first DQS rising edge
DQS input postamble after last DQS rising edge
DQS output write preamble valid time before
SDCLK[5:0] rising edge
DQS output write postamble after last DQS falling
edge
DQ[63:0] Input setup time from DQS
DQ[63:0] Input hold time from DQS
DQ[63:0], DQM[7:0] Output Data Valid Delay time
from DQS rising OR falling edge
MA[12:0], BA[1:0], CAS[1:0]#, RAS[1:0]#,
CKE[1:0], CS[3:0]#, WE[1:0] Output Valid Delay
time from SDCLK[5:0]
and t
DQSCK
timings are achieved for different DIMM loadings by proper initial settings of the
Table 7-12. Memory (DDR) Interface Signals
VAL2
.
0.5*t
-0.25*t
0.25*t
0.25*t
0.75*t
0.25*t
0.25*t
+0.5
+0.5
Min
-0.2
-0.5
-0.5
-0.4
-0.4
5.0
2.4
2.4
5.0
1.1
CK
CK
CK
-0.4
CK
CK
CK
CK
0.75*t
0.5*t
0.25*t
t
Max
+0.4
CK
0.1
0.2
0.5
3.0
CK
CK
-2
CK
+1
+1
33234C
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
Note 2
48% t
48% t
Guaranteed by
design
Note 2, Note 3
Same as t
Note 4
Note 3
Note 3
Note 3
Note 3,Note 5
Note 3, Note 5
Note 3,
Note 3, Note 4
CK
CK
CK
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