ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 199

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
5.5.2.114 FPU Modes MSR (FP_MODE_MSR)
MSR Address
Type
Reset Value
5.5.2.115 FPU Reserved MSR (FPU_RSVD_MSR)
MSR Address
Type
Reset Value
This register is reserved for internal testing; do not write.
5.5.2.116 FPU Reserved MSR (FPU_RSVD_MSR)
MSR Address
Type
Reset Value
This register is reserved for internal testing; do not write.
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:2
Bit
1
0
Name
RSVD
FPU_SP
FPU_IPE
00001A00h
R/W
00000000_00000000h
00001A01h
R/W
00000000_00000000h
00001A03h
R/W
00000000_00000000h
Description
Reserved. Write as read.
Limit Results to Single Precision. The FPU datapath width is single-precision. Opera-
tions on single precision numbers can generally be completed in one cycle, but double or
extended precision numbers takes many cycles. This bit overrides the precision control
bits in the x87 Mode Control register (of the FPU Instruction Set), and causes the FPU to
operate as if the precision control is set to single precision (00).
0: Disable.
1: Enable limit to single precision.
Enable Force of Imprecise Exceptions. For precise exceptions, the FPU allows only
one instruction to be in the pipeline at a time when any FPU exceptions are unmasked.
This results in a huge performance penalty. To run the FPU at full speed, it is necessary
to mask all exceptions in the FPU_CW_MSR (MSR 00001A10h[11:0]).
When this bit is set, the FPU is allowed to run at full speed even if there are unmasked
exceptions in the FPU_CW. With this bit set, exceptions will be generated, however,
there is no guarantee that the exception will occur on any particular instruction boundary.
It is known that setting this bit will cause some diagnostic software to fail. It is recom-
mended to be set only when the FPU exception handler does not need to handle excep-
tions on the specific instruction boundary.
0: Disable.
1: Enable.
FP_MODE_MSR Bit Descriptions
FP_MODE_MSR Register Map
RSVD
RSVD
9
8
33234C
7
6
5
4
3
2
1
199
0