ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 168

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Region Properties
The region properties consist of an 8-bit field as shown in Table 5-15. Table 5-16 and Table 5-17 describe the various region
properties effects on read and write operations. Note that the cache is always interrogated even in regions that are not
cacheable, and read hits are serviced from the cache while write hits update the cache and are sent to the bus using the
region’s write semantics.
168
WS
Note: “x” indicates setting or clearing this bit has no effect.
WS
0
1
1
0
0
0
0
1
0
x
x
x
x
7
Reserved
(RSVD)
WC
WC
x
x
x
x
x
1
x
0
0
0
0
0
1
6
WT
WT
0
0
1
0
0
0
x
x
x
x
x
x
x
(Write-serialize)
WP
WP
33234C
x
x
x
1
x
x
x
0
0
0
0
0
0
WS
5
WA
WA
x
x
x
x
x
x
1
0
1
x
0
0
0
Table 5-16. Read Operations vs. Region Properties
Table 5-17. Write Operations vs. Region Properties
Table 5-15. Region Properties Register Map
CD
CD
(Write-combine)
0
0
1
0
0
1
0
0
0
1
1
1
x
WC
Description
Cacheable. Read misses cause a cache line to be allocated.
Undefined State. Unpredictable behavior occurs.
Uncacheable. Reads are sent unmodified to the bus. Cache is still interro-
gated and provides data for read hits. Used for accessing memory-mapped
devices.
Description
Write-protected. Writes to the region are discarded.
Undefined State. Unpredictable behavior occurs.
Undefined State. Unpredictable behavior occurs.
Undefined State. Unpredictable behavior occurs.
Write-back Cacheable. Write misses are sent to the bus, a cache line is not
allocated on a write miss.
Write-back Cacheable/Write-allocate. Write misses allocate a line in the
cache.
Write-through cacheable. Write misses do not allocate a line in the cache.
Write hits update the cache but do not mark the line as dirty. All writes are sent
to the bus.
Uncacheable. All writes are sent to the bus in strict program order without any
combining. Write hits still update the cache. Traditionally used for accessing
memory-mapped devices (but see write-burstable below).
Uncacheable. All writes are sent to the bus in strict program order without any
combining. Write hits still update the cache. Traditionally used for accessing
memory-mapped devices (but see write-burstable below).
Write-serialize. Limit the number of outstanding writes to the value of the
WSREQ field in DM_CONFIG0_MSR (MSR 00001800h[46:44]).
Write-combined (uncacheable). Writes to the same cache line may be com-
bined. Multiple writes to the same byte results in a single write with the last
value specified. Write order is not preserved; ideal for use with frame buffers.
4
(Write-through)
WT
3
(Write-protect)
WP
2
AMD Geode™ LX Processors Data Book
(Write-allocate)
CPU Core Register Descriptions
WA
1
(Cache Disable)
CD
0