ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 306

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6.1.4
MSR Address
Type
Reset Value
306
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
9
8
7
6
5
4
3
2
1
0
GLD Error MSR (GLD_MSR_ERROR)
Name
GFXIOW_MSK
SEQIOR_MSK
SEQIOW_MSK
CRTCIOR_MSK
CRTCIOW_MSK
CRTCIO_MSK
VGA_BL_MSK
ISR0_MSK
MISC_MSK
VG_BL_MSK
80002003h
R/W
00000000_00000000h
33234C
Description
Graphics Controller Register Write SMI. When set to 1, disables generation of the
SMI that indicates that one or more of the VGA’s Graphics Controller registers has
been written.
Sequencer Register Read SMI. When set to 1, disables generation of the SMI that
indicates that one or more of the VGA’s Sequencer registers has been read.
Sequencer Register Write SMI. When set to 1, disables generation of the SMI that
indicates that one or more of the VGA’s Sequencer registers has been written.
CRTC Register Read SMI. When set to 1, disables generation of the SMI that indi-
cates that one or more of the VGA’s CRTC registers has been read; writing a 1 to this
bit clears it.
CRTC Register Write SMI. When set to 1, disables generation of the SMI that indi-
cates that one or more of the VGA’s CRTC registers has been written.
CRTC Invalid Register I/O SMI Mask. When set to 1, disables generation of a syn-
chronous SMI when a non-implemented VGA CRT Controller Register is read or writ-
ten.
VGA Vertical Blank SMI Mask. When set to 1, disables generation of the VGA Vertical
Blank SMI.
Input Status Register 0 SMI Mask. When set to 1, disables generation of the VGA
Input Status Register SMI.
Miscellaneous Output Register SMI Mask. When set to 1, disables generation of the
Miscellaneous Output Register synchronous SMI.
DC Vertical Blank SMI Mask. When set to 1, disables the DC Vertical Blank SMI when
set to 1.
GLD_MSR_SMI Bit Descriptions (Continued)
GLD_MSR_ERROR Register Map
RSVD
RSVD
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book
9
8
7
6
5
4
3
2
1
0