ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 506

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.10.2.30 VIP Task A U Even Offset (VIP_TASK_A_U_EVEN_OFFSET)
VIP Memory Offset 7Ch
Type
Reset Value
6.10.2.31 VIP Task A V Even Offset (VIP_TASK_A_V_EVEN_OFFSET)
VIP Memory Offset 80h
Type
Reset Value
506
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:0
31:0
Bit
Bit
Name
TASK_A_U_EV
EN_OFFSET
Name
TASK_A_V_EV
EN_OFFSET
R/W
00000000h
R/W
00000000h
33234C
VIP_TASK_A_U_EVEN_OFFSET Bit Descriptions
Description
Task A U Even Offset. This register determines the starting address of the U buffer for
the even field when in interlaced input mode and data is stored in planar format. This reg-
ister is not used when in non-interlaced input mode. The value in this register needs to be
32-byte aligned. (Bits [4:0] are required to be 00000.)
VIP_TASK_A_V_EVEN_OFFSET Bit Descriptions
Description
Task A V Even Offset. This register determines the starting address of the V buffer for
the even field when in interlaced input mode and data is stored in planar format. This reg-
ister is not used when in non-interlaced input mode. The value in this register needs to be
32-byte aligned. (Bits [4:0] are required to be 00000.)
VIP_TASK_A_U_EVEN_OFFSET Register Map
VIP_TASK_A_V_EVEN_OFFSET Register Map
TASK_A_U_EVEN_OFFSET
TASK_A_V_EVEN_OFFSET
AMD Geode™ LX Processors Data Book
9
Video Input Port Register Descriptions
9
8
8
7
7
6
6
5
5
4
Program to 00000
4
Program to 00000
3
3
2
2
1
1
0
0