ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 209

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Memory Controller
Features
• Supports up to 400 MT/S (million transfers per second)
• Supports 64-bit data interface
• Supports unbuffered DIMMs and SODIMMs
• Can maintain up to 16 open banks at a time
• Can support up to three outstanding requests at a time
• Arbiter reorders requests from different sources to opti-
• Single and burst data phase optimization
• Programmable modes of high and low order address
• Queues up to eight refreshes
• Supports low power mode
• Highly configurable to obtain best performance for
6.1.1
6.1.1.1
The GLMC module supports two address translations
depending on the method used to interleave pages. The
hardware supports High Order Interleaving (HOI) or Low
Order Interleaving (LOI). Select the interleaving mode used
by programming the HOI_LOI bit of the MC_CF8F_DATA
register (MSR 20000019h[33]. See Section 6.2.2.10 "Tim-
ing and Mode Program (MC_CF8F_DATA)" on page 227 for
bit description.
High Order Interleaving
High Order Interleaving (HOI) uses the most significant
address bits to select which bank the page is located in.
Figure 6-3 shows an example of how the Geode LX pro-
cessor’s internal physical addresses are connected to the
memory interface address lines.
This interleaving scheme works with any mixture of DIMM
types. However, it spreads the pages over wide address
ranges. For example, assume a 64 MB memory subsystem
with two 32 MB DIMMs installed. Each DIMM has a single
module bank, and each module bank contains four compo-
nent banks. This gives a total of eight component banks in
this memory configuration. Each page in a component
bank is separated from the next component bank page by
8 MB. See Figure 6-4.
AMD Geode™ LX Processors Data Book
DDR SDRAMs
mize data bus utilization
interleaving
installed DRAM
Functional Hardware
Address Translation
01800000h
01000000h
00800000h
00000000h
RA are the RAS addresses on MA[12:0]
CA are the CAS addresses on MA[7:0]
RA[12:10]
MB[1]
MB[0]
BA[1:0]
RA[9:0]
CA[7:0]
Internal
Physical
Address
Figure 6-3. HOI Addressing Example
Module Bank
Component Banks
DIMM0
Figure 6-4. HOI Example
Page 0
Page 0 16M
Page 0 8M
Page 0 0M
Bank
Bank
Bank
Bank
aaaaaaaaaaaaaaaaaaaaaaaaaa
22222222211111111110000000
87654321098765432109876543
3
2
1
0
24M
33234C
03800000h
03000000h
02800000h
02000000h
Module Bank
Component Banks
DIMM1
Page 0
Page 0 48M
Page 0 40M
Page 0 32M
Bank
Bank
Bank
Bank
3
2
1
0
56M
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