ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 87

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core
This section describes the internal operations of the AMD
Geode™ LX processor’s CPU Core from a programmer’s
point of view. It includes a description of the traditional
“core” processing and FPU operations. The integrated
function registers are described in the next chapter.
The primary register sets within the processor core include:
• Application Register Set
• System Register Set
5.1
The CPU Core is initialized when the RESET# (Reset) sig-
nal is asserted. The CPU Core is placed in real mode and
the registers listed in Table 5-1 are set to their initialized
values. RESET# invalidates and disables the CPU cache,
Note 1.
AMD Geode™ LX Processors Data Book
EAX
EBX
ECX
EDX
EBP
ESI
EDI
ESP
EFLAGS
EIP
ES
CS
SS
DS
FS
GS
IDTR
GDTR
LDTR
TR
CR0
CR2
CR3
CR4
Register
x = Undefined value.
Core Processor Initialization
Register Name
Accumulator
Base
Count
Data
Base Pointer
Source Index
Destination Index
Stack Pointer
Extended Flags
Instruction Pointer
Extra Segment
Code Segment
Stack Segment
Data Segment
Extra Segment
Extra Segment
Interrupt Descriptor Table Register
Global Descriptor Table Register
Local Descriptor Table Register
Task Register
Control Register 0
Control Register 2
Control Register 3
Control Register 4
Table 5-1. Initialized Core Register Controls
xxxxxxxxh
xxxxxxxxh
xxxx 04 [DIR0]h
00000002h
0000FFF0h
0000h
F000h
0000h
0000h
0000h
0000h
Base = 0, Limit = 3FFh
xxxxh
xxxxh
60000010h
xxxxxxxxh
xxxxxxxxh
00000000h
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
Initialized Contents
(Note 1)
and turns off paging. When RESET# is asserted, the CPU
terminates all local bus activity and all internal execution.
While RESET# is asserted, the internal pipeline is flushed
and no instruction execution or bus activity occurs.
Approximately 150 to 250 external clock cycles after
RESET# is de-asserted, the processor begins executing
instructions at the top of physical memory (address location
FFFFFFF0h). The actual number of clock cycles depends
on the clock scaling in use. Also, before execution begins,
an additional 2
requested.
Typically, an intersegment jump is placed at FFFFFFF0h.
This instruction forces the processor to begin execution in
the lowest 1 MB of address space. Table 5-1 lists the CPU
Core registers and illustrates how they are initialized.
Comments
00000000h indicates self-test passed.
DIR0 = Device ID
See Table 5-4 on page 91 for bit definitions.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to FFFF0000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
See Table 5-10 on page 94 for bit descriptions.
See Table 5-9 on page 94 for bit descriptions.
See Table 5-8 on page 94 for bit descriptions.
See Table 5-7 on page 94 for bit descriptions.
20
clock cycles are needed when self-test is
5.0CPU Core
33234C
5
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