ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 38

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.4.5
38
Signal Name
RESET#
STOP#
FRAME#
IRDY#
TRDY#
PCI Interface Signals (Continued)
33234C
AH25
AK26
AJ25
AL28
Ball
Y30
No.
Type
I/O
I/O
I/O
I/O
I
33-66 Mb/s
33-66 Mb/s
33-66 Mb/s
33-66 Mb/s
0-1 Mb/s
f
3.3
3.3
3.3
3.3
3.3
V
Description
PCI Reset. RESET# aborts all operations in
progress and places the Geode LX processor into a
reset state. RESET# forces the CPU and peripheral
functions to begin executing at a known state. All
data in the on-chip cache is invalidated upon a
reset.
RESET# is an asynchronous input, but must meet
specified setup and hold times to guarantee recog-
nition at a particular clock edge. This input is typi-
cally generated during the power-on-reset (POR)
sequence.
Target Stop. STOP# is asserted to indicate that
the current target is requesting the master to stop
the current transaction. This signal is used with
DEVSEL# to indicate retry, disconnect, or target
abort. If STOP# is sampled active while a master,
FRAME# is de-asserted and the cycle is stopped
within three SYSREFs. STOP# can be asserted
when the PCI write buffers are full or a previously
buffered cycle has not completed.
Frame. FRAME# is driven by the current master to
indicate the beginning and duration of an access.
FRAME# is asserted to indicate a bus transaction is
beginning. While FRAME# is asserted, data trans-
fers continue. When FRAME# is de-asserted, the
transaction is in the final data phase.
Initiator Ready. IRDY# is asserted to indicate that
the bus master is able to complete the current data
phase of the transaction. IRDY# is used in conjunc-
tion with TRDY#. A data phase is completed on any
SYSREF in which both IRDY# and TRDY# are
sampled asserted. During a write, IRDY# indicates
valid data is present on AD[31:0]. During a read, it
indicates the master is prepared to accept data.
Wait cycles are inserted until both IRDY# and
TRDY# are asserted together.
Target Ready. TRDY# is asserted to indicate that
the target agent is able to complete the current data
phase of the transaction. TRDY# is used in con-
junction with IRDY#. A data phase is complete on
any SYSREF in which both TRDY# and IRDY# are
sampled asserted. During a read, TRDY# indicates
that valid data is present on AD[31:0]. During a
write, it indicates the target is prepared to accept
data. Wait cycles are inserted until both IRDY# and
TRDY# are asserted together.
AMD Geode™ LX Processors Data Book
Signal Definitions