ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 83

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GLIU Register Descriptions
4.2.4.5
GLIU0
MSR Address
Type
Reset Value
See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage.
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:61
59:48
47:32
31:16
15:14
PDID1
13:0
Bit
60
P2D Swiss Cheese Descriptor (P2D_SC)
Name
PDID1
PCMP_BIZ
RSVD
WEN
REN
RSVD
PBASE
P2D_SC[0]
1000002Ch
R/W
00000000_00000000h
REN
Description
Descriptor Destination ID 1. These bits define which Port to route the request to, if it is
a ‘hit’ based on the other settings in this register.
000: Port 0 = GLIU0: GLIU; GLIU1: GLIU
001: Port 1 = GLIU0: GLMC; GLIU1: Interface to GLIU0
010: Port 2 = GLIU0: Interface to GLIU1; GLIU1: VP
011: Port 3 = GLIU0: CPU Core; GLIU1: GLCP
100: Port 4 = GLIU0: DC; GLIU1: GLPCI
101: Port 5 = GLIU0: GP; GLIU1: VIP
110: Port 6 = GLIU0: Not Used; GLIU1: SB (Security Block)
111: Port 7 = GLIU0: Not Used; GLIU1: Not Used
Compare Bizzaro Flag.
0: Consider only transactions whose Bizzaro flag is low as a potentially valid address hit.
1: Consider only transactions whose Bizarro flag is high as a potentially valid address hit.
Reserved.
Enable hits to the base for the ith 16K page for writes. When set to 1, causes the
incoming request to be routed to the port specified in PDID1 if the incoming request is a
write type.
Enable hits to the base for the ith 16K page for reads. When set to 1, causes the
incoming request to be routed to the port specified in PDID1 if the incoming request is a
read type.
Reserved.
Physical Memory Address Base for Hit. These bits form the basis of comparison with
incoming checks that the physical address supplied by the device’s request on address
bits [31:18] are equal to PBASE. Bits [17:14] of the physical address are used to choose
the ith 16K region of WEN/REN for a hit.
RSVD
A low Bizarro flag indicates a normal transaction cycle such as a memory or I/O.
A high Bizzaro flag indicates a ‘special’ transaction, such as a PCI Shutdown or Halt
cycle.
P2D_SC Bit Descriptions
P2D_SC Register Map
GLIU1
MSR Address
Type
Reset Value
P2D_SC[0]
4000002Eh
R/W
00000000_00000000h
9
8
WEN
33234C
PSCBASE
7
6
5
4
3
2
1
83
0