ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 322

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6.4.6
DC Memory Offset 028h
Type
Reset Value
This register specifies the offset at which the video V buffer starts.
Settings written to this register do not take effect until the start of the following frame or interlaced field.
6.6.4.7
DC Memory Offset 02Ch
Type
Reset Value
This register specifies the top of the frame buffer memory region to be watched for frame-dirty mode.
Settings written to this register take effect immediately.
322
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:28
31:28
27:0
27:0
Bit
Bit
RSVD
DC Video V Buffer Start Address Offset (DC_VID_V_ST_OFFSET)
DC Dirty/Valid Region Top (DC_DV_TOP)
Name
FRAME_COUNT
OFFSET
Name
RSVD
OFFSET
RSVD
R/W
xxxxxxxxh
R/W
00000000h
33234C
Description
Reserved.
Video V Buffer Start Offset. This value represents the starting location for the Video V
Buffer. The lower three bits should always be programmed as zero so that the start offset
is aligned to a QWORD boundary. A buffer for V data is only used if YUV 4:2:0 display
mode is selected (DC Memory Offset 004h [20] = 1).
Description
Frame Count. When reading this register, this field indicates the current frame count, as
determined by counting rising edges of VIP VSYNC. This value is reset to 0 when
VIP_VSYNC occurs and FRAME_CNT >= FRAME_LIMIT. It can also be written to pro-
vide a mechanism for software to synchronize activities between the VIP and the Dis-
play Controller. However, this can result in corrupted video data until the next reset of
this counter.
Video U Buffer Start Offset. This value represents the starting location for the Video U
Buffer. The lower three bits should always be programmed as zero so that the start off-
set is aligned to a QWORD boundary. A buffer for U data is only used if YUV 4:2:0 dis-
play mode is selected (DC Memory Offset 004[20] = 1).
DC_VID_U_ST_OFFSET Bit Descriptions
DC_VID_V_ST_OFFSET Bit Descriptions
DC_VID_V_ST_OFFSET Register Map
DC_DV_TOP Register Map
DV_TOP
OFFSET
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book
9
9
8
8
7
7
6
6
RSVD
5
5
4
4
3
3
2
2
1
0
1
0
0