ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 501

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Video Input Port Register Descriptions
6.10.2.21 VIP Task B U Offset (VIP_TASK_B_U_OFFSET
VIP Memory Offset 54h
Type
Reset Value
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
23:16
31:0
11:0
31:0
Bit
Bit
Name
TASK_B_V_OF
FSET
START_ODD
Name
TASK_B_U_
OFFSET
R/W
00000000h
Description
Task B V Offset. This register determines the starting address of the V buffer when data
is stored in planar format. The start of the V buffer is determined by adding the contents
of this register to that of the base address. The value in this register needs to be 32-byte
aligned. (Bits [4:0] are required to be 00000.)
Note: This register in NOT double buffered and should be initialized before start of video
capture.
Start Odd Field Detect/Duration. This register is redefined in BT.601 mode. When in
BT.601 interlaced mode, this register determines the window for field detection. The Start
bits [11:0] are the number of clocks from the leading edge of HSYNC to when the detec-
tion window begins, the duration bits [23:16] are the # of clocks that the detection window
is active. If the leading edge of VSYNC occurs within the window, the field is set to odd,
otherwise it is set to even. At the default state of 0, the leading edge of VBLANK must
transition simultaneously with the leading edge of HSYNC for odd field detection. When
the NI bit in (VIP Memory Offset 00h[19]) is set (non-interlaced mode), all frames are
considered to be odd fields.
Description
Task B U Offset. This register determines the starting address of the U buffer when data
is stored in planar format. The start of the U buffer is determined by adding the contents
of this register to that of the base address. The value in this register must be 32-byte
aligned. (Bits [4:0] are required to be 00000.)
Note: This register in NOT double buffered and should be initialized before start of video
capture.
VIP_TASK_B_U_OFFSET Bit Descriptions
VIP_TAS_B_V_OFFSET Bit Descriptions
VIP_TASK_B_U_OFFSET Register Map
TASK_B_U_OFFSET
)
9
8
33234C
7
6
5
4
Program to 00000
3
2
1
501
0