ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 15

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Architecture Overview
The CPU Core provides maximum compatibility with the
vast amount of Internet content available while the intelli-
gent integration of several other functions, including graph-
ics, makes the AMD Geode™ LX processor a true system-
level multimedia solution.
The Geode LX processor can be divided into major func-
tional blocks (as shown in Figure 1-1 on page 11):
• CPU Core
• GeodeLink™ Control Processor
• GeodeLink Interface Units
• GeodeLink Memory Controller
• Graphics Processor
• Display Controller
• Video Processor
• Video Input Port
• GeodeLink PCI Bridge
• Security Block
2.1
The x86 core consists of an Integer Unit, cache memory
subsystem, and an x87 compatible FPU (Floating Point
Unit). The Integer Unit contains the instruction pipeline and
associated logic. The memory subsystem contains the
instruction and data caches, translation look-aside buffers
(TLBs), and an interface to the GeodeLink Interface Units
(GLIUs).
The instruction set supported by the core is a combination
of Intel’s Pentium
Athlon
instructions. Specifically, it supports the Pentium, Pentium
Pro, 3DNow! technology for the AMD-K6 and Athlon pro-
cessors, and MMX
supports a subset of the specialized Geode LX processor
instructions including special SMM instructions. The CPU
Core does not support the entire Katmai New Instruction
(KNI) set as implemented in the Pentium 3. It does support
the MMX instructions for the Athlon processor, which are a
subset of the Pentium 3 KNI instructions.
AMD Geode™ LX Processors Data Book
— TFT Controller/Video Output Port
™
FPU, and the AMD Geode LX processor specific
CPU Core
®
®
, the AMD-K6
instructions for the Athlon processor. It
®
microprocessor and the
2.0Architecture Overview
2.1.1
The Integer Unit consists of a single issue 8-stage pipeline
and all the necessary support hardware to keep the pipe-
line running efficiently.
The instruction pipeline in the integer unit consists of eight
stages:
1)
2)
3)
4)
5)
6)
7)
8)
Instruction Prefetch - Raw instruction data is fetched
from the instruction memory cache.
Instruction Pre-decode - Prefix bytes are extracted
from raw instruction data. This decode looks-ahead to
the next instruction and the bubble can be squashed if
the pipeline stalls down stream.
Instruction Decode - Performs full decode of instruc-
tion data. Indicates instruction length back to the
Prefetch Unit, allowing the Prefetch Unit to shift the
appropriate number of bytes to the beginning of the
next instruction.
Instruction Queue - FIFO containing decoded x86
instructions. Allows Instruction Decode to proceed
even if the pipeline is stalled downstream. Register
reads for data operand address calculations are per-
formed during this stage.
Address Calculation #1 - Computes linear address of
operand data (if required) and issues request to the
Data Memory Cache. Microcode can take over the
pipeline and inject a micro-box here if multi-box
instructions require additional data operands.
Address Calculation #2 - Operand data (if required)
is returned and set up to the Execution stage with no
bubbles if there was a data cache hit. Segment limit
checking is performed on the data operand address.
The µROM is read for setup to Execution Unit.
Execution Unit - Register and/or data memory fetch
fed through the Arithmetic Logic Unit (ALU) for arith-
metic or logical operations. µROM always fires for the
first instruction box down the pipeline. Microcode can
take over the pipeline and insert additional boxes here
if the instruction requires multiple Execution Unit
stages to complete.
Writeback - Results of the Execution Unit stages are
written to the register file or to data memory.
Integer Unit
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2
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