ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 314

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

314
11:8
Bit
7
6
5
4
3
2
1
0
Name
DFHPSL
VGAE
DECE
CMPE
FILT_SIG_SEL
VIDE
CLR_CUR
CURE
DFLE
33234C
DC_GENERAL_CFG Bit Descriptions (Continued)
Description
Display-FIFO High Priority Start Level. This field specifies the depth of the display
FIFO (in multiples of 256 bytes) at which a high-priority request is sent to the memory
controller to fill up the FIFO. The value is dependent upon display mode. This field should
always be non-zero and should be less than the high-priority end level. Note that the set-
tings in the DC_ARB_CFG register (DC Memory Offset 00Ch) can also affect the priority
of requests.
VGA Enable. When changing the state of this bit, both the DC and VGA should be
stopped, and not actively fetching and displaying data.
No other DC features operate with the VGA pass-through feature enabled, with the
exception of the CRC/signature feature, the filters, and the timing generator (when the fil-
ters or VGA fixed timings are enabled). All other features should be turned off to prevent
interference with VGA operation.
0: Normal DC operation.
1: Allow the hardware VGA use of the display FIFO and the memory request interface.
Decompression Enable.
0: Disable display refresh decompression.
1: Enable display refresh decompression.
Compression Enable.
0: Disable display refresh compression.
1: Enable display refresh compression.
Filter Signature Select. When bit 23 is clear and this bit is set, the CRC mechanism at
the output of the scaler filter (before the flicker filter) is enabled. Setting this bit when bit
23 is also set has no effect. When both this bit and bit 23 are cleared, the CRC is taken at
the output of the DC, including the border/overscan pixels. Also note that the CRC calcu-
lation can be affected by the VBI CRC enable bit, located in DC_VBI_EVEN_CTL (DC
Memory Offset 0A0h[31].
Video Enable.
0: Disable video port/overlay.
1: Enable video port/overlay.
Color Cursor.
0: 2-bpp format.
1: 32-bpp color cursor.
Cursor Enable.
0: Disable hardware cursor.
1: Enable hardware cursor.
Display-FIFO Load Enable.
0: Disable display FIFO.
1: Enable display FIFO. Setting this bit high initiates display refresh requests to the mem-
The VGA HSYNC, VSYNC, blank, and pixel outputs are routed through the back end
of the DC pixel and sync pipeline and then to the I/O pads.
ory controller at the trailing edge of vertical sync.
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book