ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 423

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Video Processor Register Descriptions
Note 1. V_TOTAL and V_SYNC_END are the values written in the Display Controller module registers.
6.8.3.5
VP Memory Offset 020h
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:32
29:16
10:0
Bit
Bit
31
30
15
14
13
Video Scale (SCL)
Name
VID_Y_START
RSVD (RO)
GP (RO)
GB (RO)
RSVD
SP
DHD
COED
Name
R/W
00000000_00000000h
RSVD
Description
Video Y Start Position. Represents the vertical start position of the video window. This
register is programmed relative to CRT Vertical sync input (not the physical screen posi-
tion). This value is calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 1. (Note 1)
Description
Reserved (Read Only). Reads back as 0.
GLIU Passed (Read Only). This bit set indicates the GLIU line buffer fill has been
passed by the Dot display. Screen display tearing might occur. This bit clears on read.
This bit is typically set if during vertical downscale, the 2nd line buffer fill hasn’t started
before the Dot display has started. This indicates an error in that the GLIU line buffer fill
can’t keep up with the Dot clock display rate.
GLIU Behind (Read Only). This bit set indicates the GLIU line buffer fill is falling behind
the Dot display. This bit clears on read.
This bit is typically set if during vertical downscale, the 2nd line buffer fill has not com-
pleted before the Dot display has started. This does not necessarily indicate an error,
recovery is possible.
Reserved.
Spare. Bit is R/W but has no function.
Double Horizontal Downscale. Selects which method data gets written into line buffers.
0: Write data from video interface directly.
1: Write data from video interface averaged each 2 pixels.
This bit should only be set when horizontal downscale greater than 4:1 is desired.
Coefficient Mode. Selects between 128 and 256 coefficient usage.
0: Use common 256 vert/horz coefficient table.
1: Use separate 128 vert/horz coefficient tables.
When using separate tables, the vertical coefficient should be placed in the lower half of
the coefficient RAM (0-127 = vertical 128-255 = horizontal).
VY Bit Descriptions (Continued)
SCL Bit Descriptions
SCL Register Map
RSVD
9
8
33234C
7
6
VSL
5
4
3
2
1
423
0