ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 667

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Instruction Set
1)
2)
3)
AMD Geode™ LX Processors Data Book
PFSRQIT1 Packed Floating-Point Reciprocal Square Root, First Iteration Step
PFRSQRT Floating-Point Reciprocal Square Root
PFRSQRTV Floating-Point Reciprocal Square Root Vector
PFSUB Packed Floating- Point Subtraction
PFSUBR Packed Floating-Point Reverse Subtraction
PI2FD Packed 32-Bit Integer to Floating-Point Conversion
PIF2W Packed Integer Word to Floating-Point Conversion
PMULHRW Multiply Signed Packed 16-bit Value with Rounding and Store the High 16 bits
PREFETCH/PREFETCHW Prefetch Cache Line into L1 Data Cache (Dcache)
PSWAPD Packed Swap Doubleword
MMX Register1 with MMX Register 2
MMX Register with Memory64
MMX Register 1 by MMX Register 2
MMX Register by Memory64
MMX Register1 with MMX Register2
MMX Register with Memory64
MMX Register1 with MMX Register2
MMX Register with MMX Memory64
MMX Register1 with MMX Register2
MMX Register with Memory64
MMX Register1 by MMX Regester2
MMX Register by Memory64
MMX Register1 by MMX Register2
MMX Register by Memory64
MMX Register1 with MMX Register2
MMX Register with Memory64
Memory 8
MMX Register1 by MMX Register2
MMX Register by Memory64
These instructions must wait for the FPU pipeline to flush. Cycle count depends on what instructions are in the pipe-
line.
The Geode LX processor performs PFRCP and PFRSQRT to 24-bit accuracy in one cycle, so these instructions are
unnecessary. They are treated as a move.
Non-standard 3DNow! instruction. See Section 8.4.1 on page 668 for details.
3DNow!™ Instructions
Table 8-30. 3DNow!™ Technology Instruction Set (Continued)
0F0F [11 mm1
mm2] A7
0F0F [mod mm r/m]
A7
0F0F [11 mm1
mm2] 97
0F0F [mod mm r/m]
97
0F0F [11 mm1
mm2] 87
0F0F [mod mm r/m]
87
0F0F [11 mm1
mm2] 9A
0F0F [mod mm r/m
9A
0F0F [11mm1 mm2]
AA
0F0F [mod mm r/m]
AA
0F0F [11 mm1
mm2] 0D
0F0F [mod mm r/m]
0D
0F0F [11 mm1
mm2] 0C
0F0F [mod mm r/m]
0C
0F0F [11 mm1 mm2
B7
0F0F [mod mm r/m
B7
0F0D
0F0F [11 mm1
mm2] BB
0F0F [mod mm r/m]
BB
Opcode/imm8
MMX reg 1 [dword] <--- move --- MMX reg 2 [dword]
MMX reg [dword] <--- move --- Memory64 [dword]
MMX reg.1 [low dword] <--- reciprocal --- square root --- MMX reg 2
[low dword]
MMX reg 2 [high dword] <--- reciprocal --- square root --- MMX reg 2
[low dword]
MMX reg [low dword] <--- reciprocal --- square root --- Memory64 [low
dword]
MMX reg [high word] <--- reciprocal --- square root --- Memory64 [low
dword]
MMX reg 1 [low dword] <--- sat --- reciprocal --- square root --- MMX
reg 2 [low dword]
MMX reg 1 [high word] <--- sat --- reciprocal --- square root --- MMX reg
2 [high dword]
MMX reg [low dword] <---sat --- reciprocal --- square root --- Memory64
[low dword]
MMX reg [high dword] <--- sat --- reciprocal --- square root ---
Memory64 [high dword]
MMX reg 1 [dword] <--- (MMX reg1 [dword] - MMX reg 2 [dword])
MMX reg [dword] <--- (MMX reg [dword] - Memory64 [dword])
MMX reg 1 [dword] <---(MMX reg 2 [dword] - MMX reg [dword])
MMX REG [dword] <--- (Memory64 [dword] - MMX reg [dword])
MMX reg 1 [dword] <--- trun --- float --- MMX reg 2 [dword]
MMX reg [dword] <--- trun --- float --- Memory64 [dword]
MMX reg 1 [low dword] <--- float --- MMX reg 2 [low word (low dword)]
MMX reg 1 [high dword] <--- float --- MMX reg 2 [low word (high dword)]
MMX reg [low dword] <--- float --- Memory64 [low word (low dword)]
MMX reg [high dword] <--- float --- Memory64 [low dword (high dword)]
MMX reg 1 [word] <--- (MMX reg 1 [word] * MMX reg 2 [word]) + 8000h
MMX reg [word] <--- (MMX reg [word] * Memory64 [word]) + 8000h
MMX reg 1 [low dword] <--- MMX reg 2 [high dword]
MMX reg 1 [high dword] <--- MMX reg 2 [low dword]
MMX reg [low dword] <--- Memory64 [high dword]
MMX reg [high dword] <--- Memory64 [low dword]
Operation
33234C
Cnt
Clk
1
2
2
2
2
2
2
2
1
Notes
1, 2
3
667