ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 534

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GIO_PCI Serial Protocol
The GIO can override the functionality of its SUSP# pin to
create a serial bus called CPU Interface Serial (CIS). The
reset mode for this pin is the SUSP# function. To properly
operate as the CIS interface, the CISM bit in MSR
51000010h[4:3] in the companion device must be pro-
grammed for Mode C. Notice that all the input signals are
active low. They are all inverted inside the GIO and con-
verted to active high signals. The protocol is shown in Table
6-84. The SUSP# pin must always be parked as inactive or
1.
Serial packets are expected whenever the companion
device signals transitions. Back to back serial packets can
occur once the entire serial packet has completed. The
Geode LX processor decoded signals are guaranteed to
transition only after the entire completion of the packet,
although they may transition during the transmission of the
packet.
SUSP#/CIS Pin Initialization
The SUSP# function must NOT be active until the initializa-
tion code can set the CISM bits in the companion device to
set the correct companion device mode.
GIO_SMI Synchronization
If the companion device generates a synchronous SMI in
response to a specific CPU initiated instruction (I/O), the
SMI# signal is transmitted to the processor before the com-
pletion of the PCI cycle. Therefore, the companion device
must not complete read or write cycles until it has transmit-
ted the SMI. The design guarantees that if the PCI cycle
completes on the PCICLK after the SMI transmission, the
SMI will reach the processor before the I/O completion
response. Therefore, the processor can handle the SMI
before completing the instruction.
GIO_A20M
GIO_A20M is emulated with an SMI. The processor
receives an SMI from the companion device on I/Os that
modify the state of A20M. The SMI handler must then write
to MSR_A20M (MSR 4C000031h) in the GIO to trigger a
real A20M signal back to the processor. When the instruc-
tion completes, A20M is asserted.
GIO_NMI
The GIO_NMI signal is the real NMI from the companion
device.
GIO_INPUT_DIS, GIO_OUTPUT_DIS
GIO_INPUT_DIS and GIO_OUTPUT_DIS are part of the
GLIU power management. See the AMD Geode™ CS5536
Companion Device Data Book for details.
GIO_INIT
GIO_INIT is triggered via MSR 4C000033h in the GLCP for
all companion device modes. INIT is used to reset the
CPU. It is NOT a CPU soft reset.
534
33234C
0 (START)
1 (START)
18 (END)
19 (END)
Phase
Table 6-84. CIS Signaling Protocol
10
11
12
13
14
15
16
17
2
3
4
5
6
7
8
9
AMD Geode™ LX Processors Data Book
GeodeLink™ Control Processor
(GIO CIS Mode C)
OUTPUT_DIS#
Bit Definition
INPUT_DIS#
SUSP#
INTR#
RSVD
RSVD
NMI#
SMI#
0
0
1
1
1
1
1
1
1
1
1
1