ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 380

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6.21.7 Color Select
Index
Type
Reset Value
6.6.22
Video DAC palette registers are accessed by writing the Palette Address register at the read or write address, then perform-
ing three reads or writes, one for each of the red, green, and blue color values. The video DAC provides an address incre-
ment feature that allows multiple sets of color triplets to be read or written without writing the Palette Address register again.
To invoke this feature, simply follow the first triplet read/write with the next triplet read/write.
The original IBM video DAC behavior for read operations is:
1)
2)
3)
4)
5)
The original IBM video DAC behavior for write operations is:
1)
2)
3)
4)
5)
380
Address
Bit
7:4
3:2
1:0
CPU initiates a palette read by writing INDEX to I/O address 3C7h.
Video DAC loads a temporary register with the value stored at palette[INDEX].
Video DAC increments INDEX (INDEX = INDEX + 1).
CPU reads red, green, blue color values from temporary register at I/O address 3C9h.
Loop to step 2.
CPU initiates a palette write by writing INDEX to I/O address 3C8h.
CPU writes red, green, blue color values to temporary DAC registers at I/O address 3C9h.
Video DAC stores the temporary register contents in palette[INDEX].
Video DAC increments INDEX (INDEX = INDEX + 1).
Loop to step 2.
3C8h
3C7h
3C7h
3C9h
3C6h
I/O
Video DAC Registers
Name
RSVD
P[7:6]
P[5:4]
14h
R/W
xxh
Type
R/W
R/W
RO
RO
RO
33234C
Register
Palette Address (Write Mode)
Palette Address (Read Mode)
DAC State
Palette Data
Pel Mask
Description
Reserved.
P7 and P6. These bits are used to provide the upper two bits of the 8-bit pixel value sent
to the video DAC in all modes except the 256 color mode (mode 13h).
P5 and P4. These bits are used to provide bits 5 and 4 of the 8-bit pixel value sent to the
video DAC when the P5:4 Select bit is set in the Attribute Mode Control register (Index
10h[7]). In this case, they replace bits [5:4] coming from the EGA palette.
Table 6-58. Video DAC Registers Summary
Color Select Register Bit Descriptions
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book
Reset Value
00h
00h
00h
00h
00h
Reference
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