ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 451

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Video Processor Register Descriptions
6.8.3.45 Power Management (PM)
FP Memory Offset 410h
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
18:16
63:32
31:28
15:0
Bit
Bit
27
26
SP
Name
PIXF
RSVD
Name
RSVD (RO)
SP
PWR_SEQ_SEL
PNL_PWR_SIM
R/W
00000000_00000002h
Description
Pixel Output Format. These bits define the pixel output format. The selection of the
pixel output format determines how the pixel data is formatted before being sent on to the
DRGB pins. These settings also determine the SHFCLK frequency for the specific panel.
000: Up to 24-bit TFT panel with one pixel per clock.
001: 18/24-bit TFT XGA panel with two pixels per clock.
010, 011, 100, 101, 110, and 111: Reserved.
Reserved. These bits are not defined.
Description
Reserved (Read Only). Reads back as 0.
Spares. Read/write; no function.
Power Sequence Select. Selects whether to use internal or external power
sequence. The power sequence controls the order in which VDDEN, the data and
control signals, and the backlight control signal DISPEN become active during power
up, and inactive during power down.
0: Use internal power sequencing (timing is controlled by bits [24:18]).
1: Use external power sequencing.
Must be written to 0.
Panel Power Sequence Test Mode. This bit should always be set to 0.
For simulating the model of the panel power sequence logic, this bit may be set to 1. It
connects the 14 MHz reference clock to the 32 Hz panel power sequence clock for
faster simulations. The hardware will not function properly if this bit is set to 1.
SHFCLK = DOTCLK.
SHFCLK = 1/2 of DOTCLK.
PT2 Bit Descriptions (Continued)
PM Bit Descriptions
PM Register Map
HDEL
RSVD
VDEL
9
SP
8
33234C
7
6
5
4
3
2
1
451
0