ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 478

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Vertical Timing Error (Frame or Address Error) /Mes-
sage Missed Error - This error indicates a frame error or
an address error. A frame error occurs when the time
between VSYNCs exceeds the window defined by the
VIP_SYNC_ERR_COUNT register (VIP Memory Offset
78h). The VIP_SYNC_ERR_COUNT register must be pro-
grammed. An address error occurs when the GLIU address
equals or exceeds the address programmed in the
VIP_MAX_ADDR register (VIP Memory Offset 14h). The
A_ERR_EN bit must be enabled (VIP Memory Offset
04h[30] = 1). An address error causes data reception to
stop. The A_ERR_EN must be set to a 0 to reset the
Address Error so data reception can restart. Setting the
VRST bit in Control Register 1 also resets the Address
Error (VIP Memory Offset 00h[0].
Active Pixels Per Line Error - This error is only valid when
receiving BT.656 data. This INT indicates that the amount
of active data received between SAV and EAV codes is not
the same from one line to the next. This indicates that there
is a problem in the video input data stream.
VIP Clock Input Error - This error indicates that the VIP
input clock has stopped for 128 GLIU clocks.
Ancillary Checksum or Parity Error - This error indicates
that a checksum value on an ancillary packet was wrong or
the parity on an ancillary packet was wrong. The ancillary
parity check can be disabled by setting the ANCPEN bit to
0 (VIP Memory Offset 04h[26] = 0).
Message Buffer Full or Ancillary Threshold Packet
Count Reached - When in Message Passing mode, this
indicates that a message buffer swap has occurred. The
status register can be read to find out which message
buffer has been filled. When in a video mode, this indicates
that the number of outstanding ancillary packets has
reached the threshold count programmed in VIP Memory
Offset 60h.
End of Vertical Blanking - Indicates that a falling edge of
VBLANK has occurred.
Start of Vertical Blanking - Indicates that a rising edge of
VBLANK has occurred.
Start of Even Field - Indicates that the start of the even
field has occurred (for interlaced video data only).
Start of Odd Field - Indicates that the start of the odd field
has occurred (for interlaced video data only).
Current Line = VIP Line Target - Indicates that the video
line number programmed in the VIP Current/Target register
(VIP Memory Offset 10h) has been reached.
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6.9.13
The VIP checks the input video for conditions that could
indicate an invalid data stream. These indications are pro-
vided to software via interrupts. Another component of the
video detection story is the generation of the video_ok sig-
nal to the DC. When in GenLock mode, the VIP transfers
video data to memory and synchronously to the DC
extracting the video from memory and sending it on to a
display. If the video data is interrupted, the DC needs to
know so that it can switch over to internally generated tim-
ing and data. The video_ok signal provides the indication
that the video data being received by the VIP is OK. The
ERR_DETECT bits (VIP memory Offset 00h[23:20]) are
used to enable/disable the specific checks. When an error
occurs, the video_ok signal remains 0 until the error is
reset by clearing the associated interrupt pending bit in the
VIP Interrupt register (VIP Memory Offset 0Ch). The follow-
ing checks on the video data can be performed.
• Clock Input Error - Enabled when bit 20 = 1
• Line Input Error - Enabled when bit 21 = 1
• Runaway Line Input Error - Enabled when bit 23 = 1
• Vertical Timing Error - Enabled when bit 22 = 1
• Address Error (VIP Memory Offset 04h[30] must = 1) -
Enabled when bit 22 = 1
VIP Input Video Status
AMD Geode™ LX Processors Data Book
Video Input Port