ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 198

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.5.2.112 Memory Subsystem Array Control 1 MSR (MSS_ARRAY_CTL1_MSR)
MSR Address
Type
Reset Value
5.5.2.113 Memory Subsystem Array Control 2 MSR (MSS_ARRAY_CTL2_MSR)
MSR Address
Type
Reset Value
L2 delay control settings.
198
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD
63:30
29:21
20:12
63:42
41:33
32:24
23:18
17:12
11:6
11:6
5:0
Bit
5:0
Bit
L2DATA0
Name
RSVD
IMDATA1
IMDATA0
IMTAG1
IMTAG0
Name
RSVD
L2DATA1
L2DATA0
L2TAG3
L2TAG2
L2TAG1
L2TAG0
00001982h
R/W
00000000_104823CFh
00001983h
R/W
00000104_820C30C3h
IMDATA1
33234C
Description
Reserved. (Default = 0)
Instruction Memory Subsystem Data 1 Delay Control. (Default = 82)
Instruction Memory Subsystem Data 0 Delay Control. (Default = 82)
Instruction Memory Subsystem Tag 1 Delay Control. (Default = F)
Instruction Memory Subsystem Tag 0 Delay Control. (Default = F)
Description
Reserved. (Default = 0)
L2 Cache Data 1 Delay Setting. (Default = 82)
L2 Cache Data 0 Delay Setting. (Default = 82)
L2 Cache Tag 3 Delay Setting. (Default = 3)
L2 Cache Tag 2 Delay Setting. (Default = 3)
L2 Cache Tag 1 Delay Setting. (Default = 3)
L2 Cache Tag 0 Delay Setting. (Default = 3)
MSS_ARRAY_CTL1_MSR Bit Descriptions
MSS_ARRAY_CTL2_MSR Bit Descriptions
MSS_ARRAY_CTL1_MSR Register Map
MSS_ARRAY_CTL2_MSR Register Map
L2TAG3
RSVD
IMDATA0
RSVD
L2TAG2
AMD Geode™ LX Processors Data Book
IMTAG1
L2TAG1
9
9
8
8
CPU Core Register Descriptions
7
7
6
6
L2DATA1
5
5
4
4
IMTAG0
L2TAG0
3
3
2
2
1
1
0
0