ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 498

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.10.2.16 VIP Task B Video Odd Base/Horizontal Start (VIP_TASK_B_VID_ODD_BASE_HORIZ_START)
VIP Memory Offset 3Ch
Type
Reset Value
498
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:0
15:0
31:0
11:0
Bit
Bit
Name
TASK_B_VID_
EVEN_BASE
HORIZ_END
Name
TASK_B_VID_O
DD_BASE
HORIZ_START
R/W
00000000h
33234C
VIP_TASK_B_VID_ODD_BASE_HORIZ_START Bit Descriptions
VIP_TASK_B_VID_EVEN_BASE_HORIZ_END Bit Descriptions
VIP_TASK_B_VID_ODD_BASE_HORIZ_START Register Map
Description
Task B Video Even Base Address. This register specifies the base address in graphics
memory where even video field data are stored. Changes to this register take effect at
the beginning of the next field. The value in this register is 16-byte aligned. Bits [3:0] are
always 0, and define the required address space.
Note: This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the Base Register Not Updated bit
(VIP Memory Offset 08h[16]) is set to 1. The Task B Video Even Base Address register is
not updated at this point. When the first data of the next field is captured, the pending val-
ues of all base registers are written to the appropriate base registers, and the Base Reg-
ister Not Updated bit is cleared.
Horizontal End. This register is redefined in BT.601 mode. In BT. 601 type input modes
timing is derived from the external HSYNC and VSYNC inputs. This value specifies
where video data ends for the line.
Description
Task B Video Odd Base Address. This register specifies the base address in graphics
memory where odd video field data is stored. Changes to this register take effect at the
beginning of the next field. This value must be 32-byte aligned. (Bits[4:0] are required to
be 00000.)
Note: This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the “Base Register Not Updated”
bit (VIP Memory Offset 08h[16]) is set to 1. The Video Data Odd Base Address register is
not updated at this point. When the first data of the next field is captured, the pending val-
ues of all base registers are written to the appropriate base registers, and the Base Reg-
ister Not Updated bit is cleared.
Horizontal Start. This register is redefined in BT.601 mode. In BT.601 type input modes
timing is derived from the external HSYNC and VSYNC inputs. This value specifies
where video data starts for the line. See Figure 6-47 "BT.601 Mode Horizontal Timing" on
page 469 for programing information.
TASK_B_VID_ODD_BASE_HORIZ_START (601 type modes)
AMD Geode™ LX Processors Data Book
Video Input Port Register Descriptions
9
8
7
6
5
4
3
2
1
0