ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 156

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.5.2.61 Instruction Memory Subsystem BIST Tag MSR (IM_BIST_TAG_MSR)
MSR Address
Type
Reset Value
The Instruction Memory subsystem supports built-in self-test (BIST) for the tag and data arrays. Normally, BIST is run dur-
ing manufacturing test. For convenience, BIST can be activated by reading the BIST MSRs.
WARNING: It is important that the instruction cache be disabled before initiating BIST via MSRs. There are no guarantees
of proper behavior if BIST is activated with the instruction cache enabled. The instruction cache can be disabled through
the IM_CONFIG_MSR (MSR 00001700h[4]).
5.5.2.62 Instruction Memory Subsystem BIST Data MSR (IM_BIST_DATA_MSR)
MSR Address
Type
Reset Value
156
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:2
63:1
Bits
Bits
1
0
0
Name
RSVD (RO)
CMP
TAG
Name
RSVD (RO)
DATA
00001730h
RO
00000000_0000000xh
00001731h
RO
00000000_0000000xh
33234C
Description
Reserved (Read Only). (Default = 0)
Tag Compare Logic BIST.
0: Fail (Default)
1: Pass
Valid and Tag Array BIST.
0: Fail (Default)
1: Pass
Description
Reserved (Read Only). (Default = 0)
Data Array BIST.
0: Fail
1: Pass
IM_BIST_DATA_MSR Bit Descriptions
IM_BIST_TAG_MSR Bit Descriptions
IM_BIST_DATA_MSR Register Map
IM_BIST_TAG_MSR Register Map
RSVD
RSVD
RSVD
RSVD
AMD Geode™ LX Processors Data Book
9
9
8
8
CPU Core Register Descriptions
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0