ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 229

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Memory Controller Register Descriptions
6.2.2.11 Feature Enables (MC_CF1017_DATA)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:30
29:28
26:24
23:21
20:16
11:8
15:8
Bit
7:6
5:4
2:0
Bit
7:3
27
3
Name
ACT2ACT
DPLWR
DPLRD
RSVD
RSVD
Name
RSVD
WRITE_TO_RD
RSVD
RD_TMG_CTL
RSVD
REF2ACT
PM1_UP_DLY
RSVD
2000001Ah
R/W
00000000_11080001h
Description
ACT(0) to ACT(1) Period. tRRD. Minimum number of SDRAM clocks between ACT and
ACT command to two different component banks within the same module bank. (Default
= 7h)
Data-in to PRE Period. tDPLW. Minimum number of clocks from last write data to pre-
charge command on the same component bank. (3..1 valid). Default = 10)
Data-in to PRE Period. tDPLR. Minimum number of clocks from last read data to pre-
charge command on the same component bank.(3..1 valid) The count starts on the same
clock that the last data would have been if the command was a write. (Default = 10)
Reserved.
Reserved.
RSVD
MC_CF8F_DATA Bit Descriptions (Continued)
Description
Reserved.
Write to Read Delay. tWTR. Minimum number of SDCLKS between last write data
beat to next read command. (Default = 01)
Reserved.
Read Timing Control. Number of half-GLIU clocks that the read data is delayed in
arriving at the GLMC beyond the CAS latency delay. This number increases as the
round-trip read delay increases. (Default = 001)
Reserved.
Refresh to Activate Delay. tRFC. Minimum number of SDCLKS (0-31) between
refresh and next command, usually an activate. (Default = 8h)
PMode1 Up Delay. Sets the delay in DRAM clocks from exit from PMode1 to accep-
tance of the next GLIU memory request. PMode1 power down involves a self-refresh
command to DRAM. This is to satisfy a 200-clock delay from self-refresh exit to first
read command (although this bit will delay all commands, read and write). (Default = 0,
No delay)
Reserved.
MC_CF1017_DATA Bit Descriptions
MC_CF1017_DATA Register Map
REF2ACT
RSVD
PM1_UP_DLY
9
8
33234C
7
6
RSVD
5
4
3
2
WR2DAT
1
229
0