ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 519

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Security Block Register Descriptions
6.12.3.3 SB AES Interrupt (SB_AES_INT)
SB Memory Offset 008h
Type
Reset Value
6.12.3.4 SB Source A (SB_SOURCE_A)
SB Memory Offset 010h
Type
Reset Value
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:19
18:16
15:3
31:4
Bit
2:0
Bit
3:0
SOURCE_A
Name
RSVD
INT_STATUS
RSVD
INT_MASK
Name
RSVD
R/W
00000007h
R/W
00000000h
RSVD
Description
Source A. The Source field is a 32-bit pointer to system memory. It points to the start of
data to be encrypted or decrypted. The lower four bits must be written as zero and
always read zero. This forces the data fetching to begin on a 16-byte boundary. This
register should not be changed during an AES encryption or decryption operation using
the A pointer (i.e., while STA is asserted, SB Memory Offset 000h[0] = 1). This register
can be modified during an operation using the B pointer set (while STB is asserted, SB
Memory Offset 004h[0] = 1).
Reserved. Set to 0.
Description
Reserved.
AES Interrupt Status.
0: INT not pending.
1: INT pending.
Writing a 1 to this bit clears the status.
18: EEPROM operation complete.
17: AES context B complete.
16: AES context A complete.
Reserved.
AES Interrupt Mask.
0: Enable, unmask the INT.
1: Disabled, mask the INT.
2: When enabled (0), allows EEPROM operation complete INT.
1: When enabled (0), allows AES context B complete INT.
0: When enabled (0), allows AES context A complete INT.
SB_SOURCE_A Register Bit Descriptions
SB_AES_INT Register Bit Descriptions
SB_SOURCE_A Register Map
SB_AES_INT Register Map
SOURCE_A
INT_STATUS
17
16 15 14 13 12 11 10
RSVD
9
9
8
8
33234C
7
7
6
6
5
5
4
4
3
3
INT_MASK
2
RSVD
2
1
1
519
0
0