ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 575

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ PCI Bridge Register Descriptions
6.16.2
6.16.2.1 GLPCI Global Control (GLPCI_CTRL)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:60
59:56
55:52
51:49
48:46
45:43
Bit
FTH
GLPCI Specific Registers
Name
FTH
RTH
SBRTH
RTL
DTL
WTO
50002010h
R/W
44000000_00000000h
RTH
Description
In-Bound Flush Threshold. Controls the timing for requesting new read data while con-
currently flushing previously prefetched, stale read data. If the number of prefetched 64-
bit WORDs reaches this level then a pending request will be made.
In-Bound Read Threshold. Controls the timing for prefetching read data. If the number
of prefetched 32-bit WORDs reaches this threshold, a subsequent GLIU request will be
generated to fetch the next cache line of read data.
Southbridge In-Bound Read Threshold. Controls the timing for prefetching read data
for the Geode™ companion device. If the number of prefetched 32-bit WORDs reaches
this threshold, a subsequent GLIU request will be generated to fetch the next cache line
of read data. The status of the companion device’s GNT# pin (GNT2#) is sampled to
determine when the companion device is generating an in-bound request.
Retry Transaction Limit. Limits the number of out-bound retries. If a target signals retry
indefinitely, the PCI interface may be configured to abort the failing out-bound request.
000: No limit
001: 8 retries
010: 16 retries
011: 32 retries
Delayed Transaction Limit. Limits the duration of delayed transactions. Once a read
transaction is delayed (retried before the first data phase has completed) all other in-
bound transactions are rejected until the original request is satisfied. If the original master
stops retrying, a live-lock condition may occur. If the number of rejected transactions
reaches the limit defined by this field, then the delayed transaction is forgotten.
000: No limit
001: 2 rejections
010: 4 rejections
011: 8 rejections
In-Bound Write Timeout. Controls the flushing of in-bound posted write data. When an
in-bound write has completed on the PCI bus, an internal counter is loaded with a value
derived from this field. It will then count down on each PCI clock edge. When the counter
reaches 0, the posted write data is flushed to memory.
000: 4 PCI clock edge
001: 8 PCI clock edge
010: 16 PCI clock edge
011: 32 PCI clock edges
SUS
SBRTH
GLPCI_CTRL Bit Descriptions
GLPCI_CTRL Register Map
IRFT
RTL
IRFC
DTL
IOD
WTO
100: 64 retries
101: 128 retries
110: 256 retries
111: 512 retries
100: 16 rejections
101: 32 rejections
110: 64 rejections
111: 128 rejections
100: 64 PCI clock edges
101: 128 PCI clock edges
110: 256 PCI clock edges
111: No timeout
9
ILTO
8
33234C
7
6
LAT
5
4
3
2
0
1
575
0