ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 529

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Control Processor
6.13
The GeodeLink Control Processor (GLCP) functionality
covers these areas (see Figure 6-55):
• Scan chain control
• JTAG interface to boundary scan, BIST, GLIU1, and
• Power (clock) control
• Reset logic
• PLL control
• Internal logic analyzer/debugger
• 1KB FIFO/SRAM
• Compliant with GLIU System Architecture Specification
• Supports Geode™ CS5536 companion device interface
• Supports physical pins for SUSPA# and IRQ13
• Supports muxed pin for SUSP#
AMD Geode™ LX Processors Data Book
GIO_IGNNE
GIO_INTR
VA_FERR
debug logic
v1.07
GIO_INIT
GIO_NMI
SUSPA#
SUSP#
IRQ13
INTA#
TCLK
TMS
TDO
TDI
GeodeLink™ Control Processor
PCI Clock Frequency
GLIU Clock Frequency
Synchronizing
Companion
Companion
Geode™
Geode™
rqin, rqout, dain, daout
Interface
Interface
IEEE 1149.1
Device
Device
(GIO)
(GIO)
Interface
GIO
GLIU Interface
Scan, BIST, Clock, Reset, Suspend Signals
Figure 6-55. GLCP Block Diagram
Serial-to-GLIU
Conversion
Scan and BIST
Debug Clock Frequency (varies)
TCLK Clock Frequency
Control
6.13.1
The TAP controller is IEEE 1149.1 compliant. TMS, TDI,
TCLK, and TDO are directly supported (TRST is available
as a bootstrap pin during reset, but is always inactive if the
system reset is inactive). The Instruction register(IR) is 25
bits wide. The meanings of the various instructions are
shown in Table 6-81 on page 530 along with the length of
the Data register that can be accessed once the instruction
is entered. All Data registers shift in and out data, LSB first.
The Instruction and all Data registers are shift registers, so
if more bits are shifted in than the register can hold, only
the last bits shifted in (the MSBs) are used.
The TAP controller has specific pre-assigned meanings to
the bits in the 25-bit IR. The meanings are summarized in
Table 6-82 on page 530. Note that the bits only affect the
chip once the “Update-IR” JTAG state occurs in the JTAG
controller. Shifting through these bits does not change the
state of internal signals (for example TEST_MODE). For
details on JTAG controller states, refer to the IEEE Stan-
dard 1149.1-1990.
Clock, Reset,
ACPI Control
Debug
Control
TAP Controller
TDBGI,TDBGO
Comparators
Generator
Decode
Debug
Debug
Action
Event
33234C
Data and Control Buses
Control Only
Diagnostic Bus
128 WORD
64-Bit
FIFO
Diagnostic Pins
Off-Chip
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