ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 541

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Control Processor Register Descriptions
6.14.2
6.14.2.1 GLCP Clock Disable Delay Value (GLCP_CLK_DIS_DELAY)
MSR Address
Type
Reset Value
6.14.2.2 GLCP Clock Mask for Sleep Request (GLCP_PMCLKDISABLE)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:34
63:24
23:0
Bit
33
32
31
30
Bit
GLCP Specific MSRs - GLCP Control MSRs
Name
RSVD
VIPVIP
VIPGLIU
AES
AESGLIU
RSVD
Name
RSVD
CLK_DELAY
4C000008h
R/W
00000000_00000000h
4C000009h
R/W
00000000_00000000h
Description
Reserved. Write as read.
Clock Disable Delay. If enabled in GLCP_GLB_PM (CLK_DLY_EN bit, MSR
4C00000Bh[4] = 1), indicates the period to wait from SLEEP_REQ before gating off
clocks specified in GLCP_PMCLKDISABLE (MSR 4C000009h). If this delay is enabled,
it overrides or disables the function of GLCP_CLK4ACK (MSR 4C000013h). If the
CLK_DLY_EN bit is not set, but this register is non-zero, then this register serves as a
timeout for the CLK4ACK behavior.
Description
Reserved.
VIP VIPCLK Off. When set, disables VIP VIPCLK.
VIP GLIU Clock Off. When set, disables VIP GLIU clock.
AES Core Functional Clock Off. When set, disables AES encryption/decryption
clock.
AES GLIU Clock Off. When set, disables AES GLIU interface clock.
GLCP_CLK_DIS_DELAY Bit Descriptions
GLCP_PMCLKDISABLE Bit Descriptions
GLCP_CLK_DIS_DELAY Register Map
GLCP_PMCLKDISABLE Register Map
RSVD
RSVD
CLK_DELAY
9
9
8
8
33234C
7
7
6
6
5
5
4
4
3
3
2
2
1
1
541
0
0