ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 347

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Display Controller Register Descriptions
6.6.12.5 DC Interrupt (DC_IRQ)
DC Memory Offset 0C8h
Type
Reset Value
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:27
26:16
15:11
31:18
10:0
15:2
Bit
Bit
17
16
1
0
Name
RSVD
CLR_KEY_Y_
END
RSVD
CLR_KEY_Y_
START
Name
RSVD
VIP_VSYNC_
LOSS_IRQ
IRQ
RSVD
VIP_VSYNC_
LOSS_IRQ_
MASK
IRQ_MASK
R/W
00000003h
RSVD
Description
Reserved. Set to 0.
Color Key Vertical End. This field represents the vertical end position of the color key
region minus 1. This represents the first line past the end of the color key region.
Reserved. Set to 0.
Color Key Vertical Start. This field represents the vertical start position of the color key
region minus 1. This represents the first line within the color key region.
Description
Reserved. Set to 0.
VIP VSYNC Loss IRQ. If set to 1, this field indicates that while GenLock was enabled,
GenLock timeout was enabled, and the DC reached the end of a frame and detected
VIP_VIDEO_OK (DC Memory Offset D4h[23]) inactive. As a result of this condition, the
DC began display of a field/frame based on its own timings.
IRQ Status. If set to 1, this field indicates that the vertical counter has reached the value
set in the IRQ/Filter Control Register. The state of the IRQ_MASK, bit 0, will not prevent
this bit from being set. To clear the interrupt, write a 1 to this bit.
Reserved. Set to 0.
VIP VSYNC Loss IRQ Mask. Masks generation of an interrupt in the event that the DC
reaches the end of a frame with GenLock enabled and GenLock timeout enabled and
determines that the VIP_VIDEO_OK (DC Memory Offset D4h[23]) input is inactive.
IRQ Mask. Setting this bit to 1 prevents the Display Controller from generating an inter-
rupt signal when the vertical counter reaches the value programmed in
DC_IRQ_FILT_CTL (DC Memory Offset 094h). Clearing this bit disables interrupt gener-
ation, but will NOT prevent IRQ, bit 16, from being set.
DC_CLR_KEY_Y Bit Descriptions
DC_IRQ Bit Descriptions
DC_IRQ Register Map
RSVD
9
8
33234C
7
6
5
4
3
2
1
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