ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 496

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

496
31:11
Bit
3:1
10
9
8
7
6
5
4
0
Name
RSVD
PDM
BRU
DOR
EFD
TP
VP
HP
RSVD
FR
33234C
Description
Reserved.
Planar De-interlace Mode. When set to 1, the U/V even buffers are referenced to the
Task A Video Odd Base Address (VIP Memory Offset 18h) rather then the Task A Video
Even Base Address (VIP Memory Offset 1Ch). This bit should always be set to 0. (Possi-
bly used in some de-interlacing schemes, but not likely.)
Base Register Update. When set to 1, base registers are updated at the beginning of
each field when in interlaced mode. When 0, the base registers are updated at the begin-
ning of each frame when in interlaced mode. This bit has no effect in non-interlaced
mode where start of field is the same as start of frame.
Disable Overflow Recovery. When set to 1, the overflow recovery logic is disabled. An
overflow interrupt is generated. It is then up to the software to do a FIFO reset to recover
from the overflow condition
Even Field UV Decimation. When set to 1, the U and V values of the even frame will be
discarded. (note: The DD bit (VIP Memory Offset 00h[16]) should be set to 1 or even
lines will also be decimated)
Task Polarity. When set to 1, the input TASK bit is inverted.
VSYNC Polarity. This bit is set to 1 when the VSYNC input is active high (high during
VBLANK) or 0 when the VSYNC input is active low (low during VBLANK). This is only
used for 601 type input video where HSYNC and VSYNC signals are used rather then
the SAV/EAV codes.
HSYNC Polarity. This bit is set to 1 when the HSYNC input is active high (high during
HBLANK) or 0 when the HSYNC input is active low (low during HBLANK). This is only
used for 601 type input video where HSYNC and VSYNC signals are used rather then
the SAV/EAV codes.
Reserved.
FIFO Reset. Setting this bit forces the VIP FIFO pointers and data counts to their reset
state. This might be used in cases where high GLIU latencies cause continuous FIFO
overflows, when a line overrun error occurs, or if the line offset gets corrupted which
could result in an image shift. This bit remains a 1 during the FIFO reset sequence. When
the FIFO reset sequence has completed, this bit is automatically reset to a 0.
The FIFO reset sequence consists of:
Input reception is halted.
The input and output FIFO addresses and data counts are reset.
Wait for all outstanding GLIU requests to be completed.
The FIFO Reset bit is set to 0.
Input data reception starts after the programmed run control event has occurred. (i.e.,
start of line, field, frame.)
VIP_CONTRL_REG3 Bit Descriptions
AMD Geode™ LX Processors Data Book
Video Input Port Register Descriptions