ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 271

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Graphics Processor Register Definitions
6.4.2.22 Stride (GP_CH3_MODE_STR)
GP Memory Offset 64h
Type
Reset Value
The GP_ CH3_MODE_STR register has multiple uses. The STRIDE field is used to indicate the byte width of the channel 3
bitmaps. Whenever the Y coordinate is incremented, this value is added (or subtracted if the Y bit is set) to (from) the previ-
ous start address to generate the start address for the next line. Stride values up to 64 KB minus one are supported.
The remaining fields of this register describe the type, size and source of the channel 3 data. The output of channel 3 can
be used to replace either source or pattern data into the ROP unit. The PS bit is used to select which pipe the data will be
placed on. If the FMT indicates that the incoming data is alpha, then the incoming data can be used as alpha data in the
alpha blend unit if the AS bits in the GP_RASTER_MODE (GP Memory Offset 38h[19:17]) register are set to 110. If the
BPP/FMT bits in the GP_RASTER_MODE register (bits [31:28]) indicate the output pixel is 32 bpp, then the incoming alpha
data is converted to 8 bits and is consumed at the rate of one pixel per clock. If the BPP/FMT bits are set for 16 bpp, then
the incoming alpha data is converted to 4 bits and is consumed at the rate of two pixels per clock. Alpha blending is not sup-
ported in 8-bpp mode.
Some operating systems store color data in reverse color order (Blue/Green/Red). This data can be converted into the cor-
rect display order by setting the BGR bit. This works for all input formats except for alpha, so if the incoming data is alpha,
do not set this bit.
Rotation is controlled by the RO bit. If this bit is set, the direction of rotation is determined by the X and Y bits. When this bit
is set, the GP_DST_OFFSET (GP Memory Offset 00h) should point to the upper left corner of the destination and the X
and Y bits in the GP_BLT_MODE (GP Memory Offset 40h[9,8]) should not be set. The output must be left to right, top to
bottom. The output is actually written in horizontal strips, 8, 16 or 32 pixels high and as wide as the output. For 8-bpp rota-
tion, 1K of buffer space is the minimum required to perform the operation. Having 2K available allows data to be prefetched
while the previous tile is being written out. Setting the PL bit limits the buffer size to 1K as it preserves the LUT data in the
other 1K of the buffer. This bit should be set when performing any indexed color BLT or if it is likely that the LUT data that
has been loaded will be needed again for a future BLT. The performance is higher when this bit is not set.
AMD Geode™ LX Processors Data Book
EN PS
31 30 29 28 27 26 25 24 23
31:29
28:26
23:0
Bit
Bit
25
24
31
30
X
Name
YLSBS
XLSBS
N
RSVD
OFFSET
Name
EN
PS
Y
BPP/FMT
R/W
00000000h
RO BGR PM PL PE HS RSVD
Description
Enable.
0: Channel 3 is off. Old pipelines behave exactly as they used to.
1: Channel 3 is on. Data is forced into either source or pattern pipe from channel 3.
Pipe Select.
0: Channel 3 data directed to/replaces old pattern pipeline.
1: Channel 3 data directed to/replaces old source pipeline
Description
YLSBS. Y coordinate of starting pixel within color pattern memory.
XLSBS. X coordinate of starting pixel within color pattern memory.
Nibble Select. Nibble address for 4 bpp pixels/alpha. 0 starts at the leftmost nibble, 1
starts at the rightmost.
Reserved. Write as read.
Offset. Offset from the channel 3 base address to the first source pixel.
22
GP_CH3_MODE_STR Bit Descriptions
GP_CH3_MODE_STR Register Map
GP_CH3_OFFSET Bit Descriptions
21 20 19 18 17 16 15 14 13 12 11 10
9
STRIDE
33234C
8
7
6
5
4
3
2
1
271
0