ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 500

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.10.2.19 VIP Task B Data Pitch/Vertical Start Even (VIP_TASK_B_DATA_PITCH_VERT_START_EVEN)
VIP Memory Offset 48h
Type
Reset Value
6.10.2.20 VIP Task B V Offset (VIP_TASK_B_V_Offset)
VIP Memory Offset 50h
Type
Reset Value
500
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31:28
27:16
11:0
15:0
11:0
Bit
Bit
RSVD
Name
VBI_START
Name
RSVD
VERTICAL_
END_EVEN
(even/second
field)
TASK_B_DATA
_PITCH
VERT_START_
EVEN
(even/second
field)
R/W
00000000h
R/W
00000000h
VIP_TASK_B_DATA_PITCH_VERT_START_EVEN BIT Descriptions
33234C
VIP_TASK_B_DATA_PITCH_VERT_START_EVEN Register Map
VIP_TASK_B_VBI_ODD_BASE_VBI_START BIt Descriptions
VERTICAL_END_EVEN
Description
Reserved.
Vertical End Even. This register is redefined in BT.601 mode. In BT.601 type input
modes timing is derived from the external HSYNC and VSYNC inputs. This value speci-
fies the last line of the even field captured in interlaced modes. This value is ignored
when the NI bit (VIP Memory Offset 00h[19]) is set (indicating non-interlaced input). The
VERT_END (VIP Memory Offset 6Ch[27:16]) value is used for non-interlaced modes.
See Figure 6-48 "BT.601 Mode Vertical Timing" on page 470 for additional detail.
Task B Data Pitch/. Specifies the logical width of the video data buffer. This value is
added to the start of the line address to get the address of the next line where captured
video data will be stored. The value in this register needs to be 32-byte aligned in linear
mode, and 64-byte aligned in planar mode. (In linear mode, bits [4:0] are required to be
00000. In planar mode, bits [5:0] are required to be 000000.)
Vertical Start Even. This register is redefined in BT.601 mode. In BT.601 type input
modes, timing is derived from the external HSYNC and VSYNC inputs. This value speci-
fies the line that the even field video data begins. Even field video data is captured until
Vertical End Even This value is ignored when the NI bit (VIP Memory Offset 00h[19]) is
set (indicating non-interlaced input). The VERT_START (VIP Memory Offset 6Ch) value
is used for non-interlaced modes. See Figure 6-48 "BT.601 Mode Vertical Timing" on
page 470 for additional detail.
Description
VBI Start. This register is redefined in BT.601 mode. In BT.601 type input modes, timing
is derived from the external HSYNC and VSYNC inputs. This value specifies what line
the VBI data starts in each field/frame. The start of VBI data begins when the number of
lines from the leading edge of VSYNC equals this value. See Figure 6-48 "BT.601 Mode
Vertical Timing" on page 470 for additional detail.
VIP_TASK_B_V_OFFSET Register Map
TASK_B_V_OFFSET_START_ODD
TASK_B_DATA_PITCH_VERT_START_EVEN
AMD Geode™ LX Processors Data Book
Video Input Port Register Descriptions
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0