ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 479

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Video Input Port Register Descriptions
6.10
The registers associated with the VIP are the Standard
GeodeLink Device (GLD) MSRs (accessed via the RDMSR
and WRMSR instructions) and VIP Configuration/Control
Registers. Table 6-75 and Table 6-76 are register summary
AMD Geode™ LX Processors Data Book
MSR Address
VIP Memory
54002000h
54002001h
54002002h
54002003h
54002004h
54002005h
Offset
0Ch
1Ch
2Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
Video Input Port Register Descriptions
Type
R/W
R/W
R/W
R/W
R/W
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 6-75. Standard GeodeLink™ Device MSRs Summary
Table 6-76. VIP Configuration/Control Registers Summary
Register Name
GLD Capabilities MSR (GLD_MSR_CAP)
GLD Configuration MSR
(GLD_MSR_CONFIG)
GLD SMI MSR (GLD_MSR_SMI)
GLD Error MSR (GLD_MSR_ERROR)
GLD Power Management Register
(GLD_MSR_PM)
GLD Diagnostic MSR (GLD_MSR_DIAG)
Register Name
VIP Control Register 1 (VIP_CTL_REG1)
VIP Control Register 2 (VIP_CTL_REG2)
VIP Status (VIP_STATUS)
VIP Interrupt (VIP_INT)
VIP Current/Target (VIP_CUR_TAR)
VIP Max Address (VIP_MAX_ADDR)
VIP Task A Video Even Base Address
(VIP_TASK_A_VID_EVEN_BASE)
VIP Task A Video Odd Base Address
(VIP_TASK_A_VID_ODD_BASE)
VIP Task A VBI Even Base Address
(VIP_TASK_A_VBI_EVEN_BASE)
VIP Task A VBI Odd Base Address
(VIP_TASK_A_VBI_ODD_BASE)
VIP Task A Video Pitch
(VIP_TASK_A_VID_PITCH)
VIP Control Register 3
(VIP_CONTRL_REG3)
VIP Task A V Offset
(VIP_TASK_A_V_OFFSET)
VIP Task A U Offset
(VIP_TASK_A_U_OFFSET)
tables that include reset values and page references where
the bit descriptions are provided.
The MSR address is derived from the perspective of the
CPU Core. See Section 4.1 "MSR Set" on page 45 for
more details on MSR addressing.
000000000_ 00000000h
000000000_ 00000000h
000000000_ 00000005h
000000000_ 00000000h
000000000_ xxxx7FFFh
00000000_ 0003C4xxh
Reset Value
Reset Value
FFFFFFFFh
42000001h
00000000h
xxxxFFFEh
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000020h
00000000h
00000000h
xxxxxxxxh
33234C
Reference
Reference
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