ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 90

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.3.1
The General Purpose registers are divided into four data
registers, two pointer registers, and two index registers as
shown in Table 5-2 on page 89.
The Data registers are used by the applications program-
mer to manipulate data structures and to hold the results of
logical and arithmetic operations. Different portions of gen-
eral data registers can be addressed by using different
names.
An “E” prefix identifies the complete 32-bit register. An “X”
suffix without the “E” prefix identifies the lower 16 bits of the
register.
The lower two bytes of a data register are addressed with
an “H” suffix (identifies the upper byte) or an “L” suffix (identi-
fies the lower byte). These _L and _H portions of the data
registers act as independent registers. For example, if the
AH register is written to by an instruction, the AL register
bits remain unchanged.
The Pointer and Index registers are listed below.
SI or ESI
DI or EDI
SP or ESP
BP or EBP
These registers can be addressed as 16- or 32-bit registers,
with the “E” prefix indicating 32 bits. The Pointer and Index
registers can be used as general purpose registers; how-
ever, some instructions use a fixed assignment of these
registers. For example, repeated string operations always
use ESI as the source pointer, EDI as the destination
pointer, and ECX as a counter. The instructions that use
fixed registers include multiply and divide, I/O access,
string operations, stack operations, loop, variable shift and
rotate, and translate instructions.
The CPU Core implements a stack using the ESP register.
This stack is accessed during the PUSH and POP instruc-
tions, procedure calls, procedure returns, interrupts, excep-
tions, and interrupt/exception returns. The Geode LX
processor automatically adjusts the value of the ESP dur-
ing operations that result from these instructions.
90
Type of Memory Reference
Code Fetch
Destination of PUSH, PUSHF, INT, CALL, PUSHA instructions
Source of POP, POPA, POPF, IRET, RET instructions
Destination of STOS, MOVS, REP STOS, REP MOVS instructions
Other data references with effective address using base registers of:
EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP
General Purpose Registers
Source Index
Destination Index
Stack Pointer
Base Pointer
33234C
Table 5-3. Segment Register Selection Rules
The EBP register may be used to refer to data passed on
the stack during procedure calls. Local data may also be
placed on the stack and accessed with BP. This register
provides a mechanism to access stack data in high-level
languages.
5.3.2
The 16-bit Segment registers are part of the main memory
addressing mechanism. The six segment registers are:
CS - Code Segment
DS - Data Segment
SS - Stack Segment
ES - Extra Segment
FS - Additional Data Segment
GS - Additional Data Segment
The Segment registers are used to select segments in
main memory. A segment acts as private memory for differ-
ent elements of a program such as code space, data space
and stack space. There are two segment mechanisms, one
for real and virtual 8086 operating modes and one for pro-
tected mode.
The active Segment register is selected according to the
rules listed in Table 5-3 and the type of instruction being
currently processed. In general, the DS register selector is
used for data references. Stack references use the SS reg-
ister, and instruction fetches use the CS register. While
some selections may be overridden, instruction fetches,
stack operations, and the destination write operation of
string operations cannot be overridden. Special segment-
override instruction prefixes allow the use of alternate seg-
ment registers. These segment registers include the ES,
FS, and GS registers.
5.3.3
The Instruction Pointer (EIP) register contains the offset
into the current code segment of the next instruction to be
executed. The register is normally incremented by the
length of the current instruction with each instruction exe-
cution unless it is implicitly modified through an interrupt,
exception, or an instruction that changes the sequential
execution flow (for example JMP and CALL).
Segment Registers
Instruction Pointer Register
Implied (Default)
Segment
CS
SS
SS
ES
DS
SS
AMD Geode™ LX Processors Data Book
Segment-Override
Prefix
None
None
None
None
CS, ES, FS, GS, SS
CS, DS, ES, FS, GS
CPU Core