ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 94
ALXD800EEXJ2VD
Manufacturer Part Number
ALXD800EEXJ2VD
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJ2VD.pdf
(675 pages)
Specifications of ALXD800EEXJ2VD
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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31:12
31:9
11:0
31:0
Bit
6:5
1:0
Bit
Bit
Bit
31
8
7
4
3
2
Name
RSVD
PCE
PGE
RSVD
PSE
DE
TSC
RSVD
Name
PDBR
RSVD
Name
PFLA
Name
PG
33234C
Description
Reserved. Set to 0 (always returns 0 when read).
Performance Counter Enable. Set PCE = 1 to make RDPMC available at nonzero privi-
lege levels.
Page Global Enable. Set PGE = 1 to make global pages immune to INVLPG instruc-
tions.
Reserved. Set to 0 (always returns 0 when read).
Page Size Extensions. Set PSE = 1 to enable 4 MB pages.
Debug Extensions. Set DE = 1 to enable debug extensions (i.e., DR4, DR5, and I/O
breakpoints).
Time Stamp Counter Instruction.
0: RDTSC instruction enabled for all CPL states.
1: RDTSC instruction enabled for CPL = 0 only.
Reserved. Set to 0 (always returns 0 when read).
Description
Page Directory Base Register. Identifies page directory base address on a 4 KB page
boundary.
Reserved. Set to 0.
Description
Page Fault Linear Address. With paging enabled and after a page fault, PFLA contains
the linear address of the address that caused the page fault.
Description
Paging Enable Bit. If PG = 1 and protected mode is enabled (PE = 1), paging is
enabled. After changing the state of PG, software must execute an unconditional branch
instruction (e.g., JMP, CALL) to have the change take effect.
Table 5-10. CR0 Bit Descriptions
Table 5-7. CR4 Bit Descriptions
Table 5-8. CR3 Bit Descriptions
Table 5-9. CR2 Bit Descriptions
AMD Geode™ LX Processors Data Book
CPU Core
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