ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 162

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.5.2.66 Default Region Configuration Properties MSR (RCONF_DEFAULT_MSR)
MSR Address
Type
Reset Value
Warm Start Value 04xxxxx0_1xxxxx01h
162
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Note: Region Properties: Bits [7:6] = RSVD; Bit 5 = WS; Bit 4 = WC; Bit 3 = WT; Bit 2 = WP; Bit 1 = WA; Bit 0 = CD.
63:48
47:32
31:16
63:56
55:36
35:28
15:0
27:8
Bits
Bit
7:0
DEVRP
See "Region Properties" on page 168 for further details.
ROMRP
Name
PFLOCKT2
PFLOCKT1
PFLOCKT0
PFLOCKNTA
Name
ROMRP
ROMBASE
DEVRP
SYSTOP
SYSRP
00001808h
R/W
01FFFFF0_10000001h
33234C
Description
Prefetch Lockout of PREFETCHT2. Bit mask of ways that cannot be allocated or
replaced on a data prefetch miss on a PREFECTHT2 instruction. If all ways are locked,
PREFETCHT2 is effectively disabled. Use this field to prevent data prefetch operations
from polluting too much of the cache. (Default = 0)
Prefetch Lockout of PREFETCHT1. Bit mask of ways that cannot be allocated or
replaced on a data prefetch miss on a PREFECTHT1 instruction. If all ways are locked,
PREFETCHT1 is effectively disabled. Use this field to prevent data prefetch operations
from polluting too much of the cache. (Default = 0)
Prefetch Lockout of PREFETCHT0. Bit mask of ways that cannot be allocated or
replaced on a data prefetch miss on a PREFECTHT0 instruction. If all ways are locked,
PREFETCHT0 is effectively disabled. Use this field to prevent data prefetch operations
from polluting too much of the cache. (Default = 0)
Prefetch Lockout of PREFETCHNTA. Bit mask of ways that cannot be allocated or
replaced on a data prefetch miss on a PREFECTHNTA instruction. If all ways are locked,
PREFETCHNTA is effectively disabled. Use this field to prevent data prefetch operations
from polluting too much of the cache. (Default = 0)
Description
ROM Region Properties. Region properties for addresses greater than ROMBASE (bits
55:36]).
ROM Base Address. Base address for boot ROM. This field represents A[32:12] of the
memory address space, 4 KB granularity.
SYSTOP to ROMBASE Region Properties. Region properties for addresses less than
ROMBASE (bits 55:36]) and addresses greater than or equal to SYSTOP (bits [27:8]).
Top of System Memory. Top of system memory that is available for general processor
use. The frame buffer and other private memory areas are located above SYSTOP.
System Memory Region Properties. Region properties for addresses less than SYS-
TOP (bits [27:8]). Note that Region Configuration 000A0000h-000FFFFFh takes prece-
dence over SYSRP.
RCONF_DEFAULT_MSR Bit Descriptions
RCONF_DEFAULT_MSR Register Map
DM_PFLOCK_MSR Bit Descriptions
SYSTOP
ROMBASE
AMD Geode™ LX Processors Data Book
9
8
CPU Core Register Descriptions
7
6
5
SYSRP
4
3
DEVRP
2
1
0