ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 340

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6.10.2 DC IRQ/Filter Control (DC_IRQ_FILT_CTL)
DC Memory Offset 094h
Type
Reset Value
340
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
30:29
26:16
Bit
31
28
27
15
14
13
12
Name
RSVD
LINEBUF_SEL
INTERLACE_
ADDRESSING
RSVD
LINE_COUNT
RSVD
ALPHA_FILT_
ENA
RSVD
FILT_ENA
R/W
00000000h
33234C
Description
Reserved.
Line Buffer Select. When LINEBUF_REG_EN[0] is set (bit 9 = 1), the coefficient RAM
address bits (FILT_ADDR, bits [7:0) and the Filter Coefficient Data registers (DC Memory
Offset 098h and 09Ch) can be used to read and write the line buffer or flicker filter RAMs.
This field selects which of the three line buffer RAMS (or two flicker filter RAMs) is to be
accessed.
Interlace Addressing. This bit indicates whether each field should be vertically deci-
mated when interlacing. If this bit is set, each field of the interlaced frame will include
every other line of the original (unscaled) frame buffer image. The flicker filter and scaler
filter should both be disabled if this bit is set.
Reserved.
Interrupt Line Count. This value determines which scan line will trigger a line count
interrupt. When the DC’s display engine reaches the line number determined by this
value, it will assert an interrupt if IRQ_MASK is cleared (DC Memory Offset 0C8h[0] = 0).
Reserved.
Alpha Filter Enable. Settings written to this field will not take effect until the start of the
following frame or interlaced field.
Setting this bit to 1 enables the scaler filter for the alpha channel. This filter is provided to
support scaling and interlacing of graphics data. If the graphics filter is disabled or this bit
is cleared, the alpha channel is not filtered; a nearest-neighbor mechanism is used
instead. This can provide cleaner transitions between regions with significantly different
alpha values.
Reserved.
Graphics Filter Enable. Settings written to this field will not take effect until the start of
the following frame or interlaced field.
Setting this bit to 1 enables the graphics scaler filter; This filter is provided to support
scaling and interlacing of graphics data.
LINE_COUNT
DC_IRQ_FILT_CTL Bit Descriptions
DC_IRQ_FILT_CTL Register Map
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book
RSVD
9
8
7
6
5
FILT_ADDR
4
3
2
1
0