ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 323

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Display Controller Register Descriptions
6.6.4.8
DC Memory Offset 030h
Type
Reset Value
This register specifies the number of bytes to transfer for a line of frame buffer, compression buffer, and video buffer data.
The compressed line buffer is invalidated if it exceeds the CB_LINE_SIZE (bits [18:12]).
Settings written to this register do not take effect until the start of the following frame or interlaced field.
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD
31:24
23:10
31:30
29:20
18:12
11:10
Bit
9:1
Bit
9:0
19
0
DC Line Size (DC_LINE_SIZE)
Name
RSVD
DV_TOP_ADDR
RSVD
DV_TOP_EN
Name
RSVD
VID_LINE_SIZE
RSVD
CB_LINE_SIZE
RSVD
FB_LINE_SIZE
VID_LINE_SIZE
R/W
xxxxxxxxh
Description
Reserved. These bits should be programmed to zero.
Dirty/Valid Region Top Address. When enabled via bit 0 (DV_TOP_EN), this field indi-
cates the size of the region to be watched for frame buffer accesses. When writes to this
region occur and the compression logic is in frame-dirty mode, the frame is marked as
dirty. (Writes outside this region, regardless of the settings in the DV_CTL register (DC
Memory Offset 088h), do not cause the frame to be marked as dirty in frame-dirty mode.)
The bits in this field correspond to address bits [23:10].
Reserved. These bits should be programmed to zero.
Dirty/Valid Region Top Enable. This bit enables the top-of-region check for frame-dirty
mode. This bit should be cleared if the compression logic is NOT configured for frame-
dirty mode.
Description
Reserved. These bits should be programmed to zero.
Video Line Size. This value specifies the number of QWORDs (8-byte segments) to
transfer for each source line from the video buffer in YUV 4:2:2 mode. In YUV 4:2:0
mode, it specifies the number of QWORDs to transfer for the U or V stream for a source
line (2x this amount is transferred for the Y stream). In YUV 4:2:2 mode, this field must be
set to a multiple of four QWORDs -- bits [21:20] must be 0.
Reserved. This bit should be programmed to zero.
Compressed Display Buffer Line Size. This value represents the number of QWORDs
for a valid compressed line plus 1. It is used to detect an overflow of the compressed
data FIFO. When the compression data for a line reaches CB_LINE_SIZE QWORDs, the
line is deemed incompressible. Note that DC actually writes CB_LINE_SIZE + 4
QWORDs to memory, so if X QWORDs are allocated for each compression line, then X -
4 + 1 (or X - 3) should be programmed into this register. Note also that the
CB_LINE_SIZE field should never be larger than 65 (041h) since the maximum size of
the compressed data FIFO is 64 QWORDs.
Reserved. These bits should be programmed to zero.
Frame Buffer Line Size. This value specifies the number of QWORDs (8-byte seg-
ments) to transfer for each display line from the frame buffer.
DC_LINE_SIZE Bit Descriptions
DC_DV_TOP Bit Descriptions
DC_LINE_SIZE Register Map
CB_LINE_SIZE
RSVD
9
8
33234C
7
FB_LINE_SIZE
6
5
4
3
2
1
323
0