ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 184

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.5.2.94 TSC and RTSC Low DWORDs MSR (RTSC_TSC_MSR)
MSR Address
Type
Reset Value
5.5.2.95 L2 Cache Configuration MSR (L2_CONFIG_MSR)
MSR Address
Type
Reset Value
L2_CONFIG_MSR controls the behavior of the L2 cache.
184
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:32
63:0
31:0
Bit
Bit
Name
RTSC
Name
RTSC_LOW
TSC_LOW
00001911h
RO
00000000_00000000h
00001920h
R/W
00000000_0000000Eh
33234C
Description
Real Time Stamp Counter. This register is the 64-bit secondary, or “real” time stamp
counter. This counter allows software to configure the TSC not to include SMM or DMM
time, and still have an accurate real time measurement that includes these times.
BC_CONFIG0_MSR (MSR 00001900h) contains configuration bits that determine if the
RTSC counts during Suspend mode. It always counts during SMM and DMM modes.
All bits in this register are writable, unlike the TSC that clears the upper DWORD to 0 on
writes.
Description
Real Time Stamp Counter Low DWORD. This field provides a synchronized snapshot
of the low DWORD of the RTSC register (MSR 00001910h).
Time Stamp Counter Low DWORD. This field provides a synchronized snapshot of the
low DWORD of the TSC register (MSR 00000010h).
RTSC_TSC_MSR Bit Descriptions
RTSC_TSC_MSR Register Map
RTSC_MSR Bit Descriptions
RTSC_LOW
TSC_LOW
AMD Geode™ LX Processors Data Book
9
8
CPU Core Register Descriptions
7
6
5
4
3
2
1
0