ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 243

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Graphics Processor
6.3.2.8
Channel 3 also supports host source data writes. When the
HS bit is set in the GP_CH3_MODE_STR register (GP
Memory Offset 64h[18]), the channel 3 fetch engine is dis-
abled and the FIFOs are filled via register writes to the
GP_CH3_HSRC register (GP Memory Offset 6Ch) or its
aliased space. If the PL bit in the GP_CH3_MODE_STR
register (GP Memory Offset 64h[20]) is not set then the GP
can accept 2 KB of data through host source writes before
its buffers are full. However, since monochrome is not sup-
ported on this channel, the output flow rate of data closely
matches the input flow (worst case is 8:1 if output is 32 bpp
and input is 4 bpp) so it is unlikely that the GP will ever fill
up. If it does fill its 2K buffer, then writes from the GLIU will
be disabled until there is space available to store it. Soft-
ware should not have to poll this interface to keep from
overrunning the FIFOs. It should be noted that, while it is
possible to program the GP to accept host source data on
both the source channel and channel 3, this should not be
done unless one of the channels is filled through the com-
mand buffer and the other through direct writes to the reg-
ister. If this is the case, it is recommended that the source
channel be filled through the command buffer and channel
3 be filled through register writes, since this will eliminate
polling and provide higher performance. It will probably
require less memory as well since the data into the source
channel will likely be monochrome and fit into a smaller
command buffer.
6.3.2.9
Software should try to setup the BLTs to use channel 3
whenever possible. This channel is designed to have the
highest performance, since it is capable of prefetching
great quantities of data even before a BLT actually starts.
This channel must be used when performing rotating BLTs,
color depth conversions, palettized color, or 8x8 color pat-
terns. This channel can carry source data, destination data,
per-pixel alpha data, or pattern data. This channel cannot
be used for monochrome data, and cannot be used for
source or destination data if it must be ROPed with 8x8
pattern data. If the pattern does not need to be 8x8, then
the old pattern hardware should be used as this will free up
channel 3 to be used for higher performance memory
fetches and host source data.
The source channel has the next highest performance, and
should be used if two channels are necessary or if the data
cannot be carried on channel 3. This channel can be used
to fetch destination data, and the performance will be
higher than using the destination channel.
The destination channel should only be used to carry desti-
nation data when it cannot be carried on either of the other
two channels. This should only be the case when the ROP
calls for source, destination and pattern, when the opera-
tion is a vector, or when alpha requires an A and B chan-
nel. In all other cases, performance will be higher if
destination is fetched on either the source channel or chan-
nel 3.
AMD Geode™ LX Processors Data Book
Channel 3 Host Source
Channel 3 Hints
6.3.3
To perform a BLT, several registers must first be config-
ured by the driver to specify the operation of the BLT
engine. These registers specify the source and destination
offsets into the frame buffer, the width and height of the
BLT rectangle, and the raster mode or alpha blend mode.
In addition, any source colors, pattern colors, and pattern
data should be loaded before initiating a BLT.
BLTs are initiated by writing to the GP_BLT_MODE regis-
ter (GP Memory Offset 40h). This register indicates the
need for source and destination data, and defines the type
of source data, and the direction in which the BLT should
proceed. Color BLTs may be performed from left to right or
right to left, top to bottom or bottom to top. This allows data
to be transferred within the screen space without corrupting
the areas from where the data is being copied. When
monochrome source is used, however, the BLT must be
performed from left to right.
Instead of BLT buffers (L1 cache), Source Read, Destina-
tion Read, and Destination Write FIFOs are used to tempo-
rarily store the data that flows through the Graphics
Processor. Overflowing the FIFOs is not possible since the
transfer is managed by the hardware anywhere within the
16 MB frame buffer memory region. At the start of a BLT,
two cache lines of destination data and up to four cache
lines of source data are fetched (if needed). Source data is
fetched in groups of four cache lines, when possible.
Source data may either be read from within the frame
buffer memory space or received from the CPU via writes
to the GP_HST_SRC register (GP Memory Offset 48h). In
either case, the data may be monochrome or color, as
specified in the GP_BLT_MODE register (GP Memory Off-
set 40h). If no source color is specified, the contents of the
GP_SRC_COLOR_FG register (GP Memory Offset 10h) is
used as the default. For a solid fill, neither source, destina-
tion, nor pattern are required and the resulting output pixel
is derived from the contents of the GP_PAT_COLOR_0
register (GP Memory Offset 18h). The destination of the
BLT is always within the frame buffer memory region and is
always the specified color depth, never monochrome.
A bit is provided in the mode registers to allow BLTs and
vectors to be throttled. When this bit is set for a particular
operation, that operation does not begin executing until the
next time the video timing enters vertical blank (VBLANK).
This function can be used to improve 2D quality by mini-
mizing tearing that occurs when writing to the frame buffer
while the image is being drawn to the screen.
BLT Operation
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