ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 114

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.5.2.10 IF Invalidate MSR (IF_INVALIDATE_MSR)
MSR Address
Type
Reset Value
IF_INVALIDATE MSR may be used to invalidate the contents of the Tag RAMs (Level-1 COF cache), Level-0 COF cache,
and the return stack. Devices external to the CPU should issue writes to IF_INVALIDATE_MSR only if the CPU is sus-
pended or stalled.
114
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
6
5
4
3
2
1
0
Name
STRONG
RSVD
RS
RSVD
CC_INVL
RSVD
CC_L1
00001102h
W
00000000_00000000h
33234C
Description
Strong Prediction. Allow the IF to make strong predictions.
0: Disable.
1: Enable. (Default)
Note:
Reserved.
Return Stack.
0: Disable.
1: Enable. (Default)
Note:
Reserved.
COF Cache Invalidation.
0: Translation Look-aside Buffer (TLB) invalidations do not invalidate the COF cache.
(Default)
1: Whenever the TLB is invalidated, the COF cache is also invalidated.
Note:
Reserved.
Level-1 COF Cache.
0: Disable.
1: Enable. (Default)
Note:
IF_CONFIG_MSR Bit Descriptions (Continued)
IF_INVALIDATE_MSR Register Map
Enabling strong predictions may improve performance.
Enabling the return stack increases performance unless CC_L1 is enabled (bit 0
= 1), then the return stack has no effect.
Invalidating the COF cache whenever the TLB is invalidated may reduce perfor-
mance.
Enabling the L1 COF cache increases performance.
RSVD
RSVD
AMD Geode™ LX Processors Data Book
9
8
CPU Core Register Descriptions
7
6
5
4
3
2
RS CC
1
0