ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 542

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

542
Bit
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
AESEE
GLCPDBG
GLCPGLIU
GLCPPCI
VPVOP
VPDOT_2
VPDOT_1
VPDOT_0
VPGLIU_1
VPGLIU_0
PCIPCIF
PCIPCI
PCIGLIU
GLIU1_1
GLIU1_0
DCGLIU_1
DCGLIU_0
RSVD
DCDOT_0
GLIU0_1
GLIU0_0
GP
GLMC
DRAM
BC_GLIU
BC_VA
MSS
IPIPE
FPUFAST
FPUSLOW
33234C
GLCP_PMCLKDISABLE Bit Descriptions (Continued)
Description
AES EEPROM Clock Off. When set, disables AES EEPROM clock.
GLCP Debug Clock Off. When set, disables GLCP DBG logic clock.
GLCP GLIU Clock Off. When set, disables GLCP GLIU clock.
GLCP GIO PCI Clock Off. When set, disables GLCP’s GIO PCI clock.
VP VOP Clock Off. When set, disables VOP logic clock.
VP Dot Clock 2 Off. When set, disables VP Dot Clock 2 (vp_vid).
VP DOT Clock 1 Off. When set, disables VP Dot Clock 1 (lcd_pix).
VP DOT Clock 0 Off. When set, disables VP Dot Clock 0 (vp_pix).
VP GLIU Clock 1 Off. When set, disables VP GLIU Clock 1 (lcd).
VP GLIU Clock 0 Off. When set, disables VP GLIU Clock 0 (vp).
Fast PCI Clock Off. When set, disables fast PCI clock inside GLPCI block.
PCI Clock Off. When set, disables normal PCI clock inside GLPCI block.
GLPCI Clock Off. When set, disables clock entering GLPCI block.
GLIU1 Clock Off. When set, disables main clock to secondary GLIU.
GLIU1 Timer Logic Clock Off. When set, disables clock to timer logic of secondary
GLIU.
DC GLIU clock 1 Off. When set, disables DC GLIU Clock 1 (vga).
DC GLIU clock 0 Off. When set, disables DC GLIU Clock 0 (DC).
Reserved. Unused bit, reads what was written, value written has no effect.
DC Dot Clock Off. When set, disables DC Dot Clock 0 (DC).
GLIU0 Clock Off. When set, disables main clock to primary GLIU.
GLIU0 Timer Logic Clock Off. When set, disables clock to timer logic of primary
GLIU.
GP Clock Off. When set, disables GP clock (GLIU).
GLMC Clock Off. When set, disables GLIU clock to GLMC.
DRAM Clocks Off. When set, disables external DRAM clocks (and, hence, feedback
clocks).
Bus Controller Clock Off. When set, disables clock to CPU bus controller block.
CPU to Bus Controller Clock Off. When set, disables CPU clock to bus controller
block.
CPU to MSS Clock Off. When set, disables CPU clock to memory subsystem block.
CPU to IPIPE Clock Off. When set, disable CPU clock to IPIPE block.
FPU Fast Clock Off. When set, disables the fast FPU clock.
FPU Clock Off. When set, disables the slow CPU clock to FPU.
GeodeLink™ Control Processor Register Descriptions
AMD Geode™ LX Processors Data Book