ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 499

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Video Input Port Register Descriptions
6.10.2.17 VIP Task B VBI Even Base/VBI End (VIP_TASK_B_VBI_EVEN_BASE_VBI_END)
VIP Memory Offset 40h
Type
Reset Value
6.10.2.18 VIP Task B VBI Odd Base/VBI Start (VIP_TASK_B_VBI_ODD_BASE_VBI_START)
VIP Memory Offset 44h
Type
Reset Value
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:0
11:0
31:0
Bit
Bit
Name
TASK_B_VBI_D
ATA_EVEN_BA
SE_VBI_END
VBI_END
Name
TASK_B_VBI_DA
TA_ODD_BASE
R/W
00000000h
R/W
00000000h
VIP_TASK_B_VBI_ODD_BASE_VBI_START BIt Descriptions
VIP_TASK_B_VBI_EVEN_BASE_VBI_END Bit Descriptions
VIP_TASK_B_VBI_ODD_BASE_VBI_START Register Map
VIP_TASK_B_VBI_EVEN_BASE_VBI_END Register Map
TASK_B_VBI_DATA_ODD_BASE_VBI_START (for 601 type modes)
TASK_B_VBI_DATA_EVEN_BASE_VBI_END (for 601 type modes)
Description
Task B VBI Even Base Address. This register specifies the base address in graphics
memory where VBI data for even fields is stored. Changes to this register take effect at
the beginning of the next field. This value must be 32-byte aligned. (Bits [4:0] are
required to be 00000.)
Note: This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the Base Register Not Updated bit
(VIP Memory Offset 08h[16]) is set to 1. The VBI Odd Base Address register is not
updated at this point. When the first data of the next field is captured, the pending values
of all base registers are written to the appropriate base registers, and the VBI Base Reg-
ister Not Updated bit is cleared.
VBI End. This register is redefined in BT.601 mode. In BT.601 type input modes, timing
is derived from the external HSYNC and VSYNC inputs. This value specifies what line
the VBI data ends in each field/frame. The end of VBI data is reached when the number
of lines from the falling edge of VSYNC equals this value. See Figure 6-48 "BT.601 Mode
Vertical Timing" on page 470 for additional detail.
Description
Task B VBI Odd Base Address. This register specifies the base address in graphics
memory where VBI data for odd fields is stored. Changes to this register take effect at
the beginning of the next field. This value must be 32-byte aligned. (Bits [4:0] are
required to be 00000.)
Note: This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the Base Register Not Updated bit
(VIP Memory Offset 08h[16]) is set to 1. The VBI Odd Base Address register is not
updated at this point. When the first data of the next field is captured, the pending values
of all base registers are written to the appropriate base registers, and the VBI Base Reg-
ister Not Updated bit is cleared.
9
9
8
8
33234C
7
7
6
6
5
5
4
4
3
3
2
2
1
1
499
0
0