ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 268

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.4.2.16 Base Offset (GP_BASE_OFFSET)
GP Memory Offset 4Ch
Type
Reset Value
This register is used to define the physical base addresses of the regions used for all GP read and write operations to mem-
ory. Each base defines a 16 MB region that begins on a 4 MB boundary. Thus the top two bits of the offset [23:22] are
added to the base to identify the correct 4 MB region in memory for a given transfer. Because there are different bases
defined for each potential source of data, each can come from a different memory region. If a memory operation goes
beyond the 16 MB region that has been assigned, it wraps back to the beginning of the 16 MB region.
6.4.2.17 Command Top (GP_CMD_TOP)
GP Memory Offset 50h
Type
Reset Value
This register defines the starting address of the command buffer within the command buffer region. Bits [23:0] of this regis-
ter are combined with the CBASE in GLD_MSR_CONFIG (MSR A0002001h) to form the 32-bit address. This register
should only be changed when the GP is not actively executing out of the command buffer, which can be checked by reading
the CE bit in the GP_BLT_STATUS register (GP Memory Offset 44h[4]) or by verifying that GP_CMD_READ (GP Memory
Offset 58h) and GP_CMD_WRITE (GP Memory Offset 5Ch) have the same value.
268
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:22
21:12
31:24
31:0
11:2
23:5
Bit
Bit
1:0
Bit
4:0
RSVD
Name
HST_SRC
Name
DBASE
SBASE
CH3BASE
RSVD
Name
RSVD
CMD_TOP
RSVD
DBASE
R/W
01004010h
R/W
01000000h
33234C
Description
Host Source Data. Used during BLT in host source mode.
Description
Destination Base. Base address of destination data region in physical memory.
Source Base. Base address of source data region in physical memory.
Channel 3 Base. Base address of channel 3 data region in physical memory.
Reserved.
Description
Reserved. Read returns 0.
Command Top. Starting address of the command buffer in the command buffer region.
Reserved. Read returns 0.
GP_BASE_OFFSET Bit Descriptions
GP_BASE_OFFSET Register Map
GP_CMD_TOP Bit Descriptions
GP_HST_SRC Bit Descriptions
GP_CMD_TOP Register Map
SBASE
CMD_TOP
Graphics Processor Register Definitions
AMD Geode™ LX Processors Data Book
9
9
8
8
CH3BASE
7
7
6
6
5
5
4
4
3
3
RSVD
2
2
RSVD
1
1
0
0