ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 535

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Control Processor Register Descriptions
6.14
All GeodeLink Control Processor registers are Model Spe-
cific Registers (MSRs) and are accessed via the RDMSR
and WRMSR instructions.
The registers associated with the GLCP are the Standard
GeodeLink™ Device (GLD) MSRs and GLCP Specific
MSRs. Table 6-85 and Table 6-86 are register summary
AMD Geode™ LX Processors Data Book
GLCP Control MSRs
4C00000Ah
4C00000Bh
4C00000Ch
4C00000Dh
4C00000Eh
4C002000h
4C002001h
4C002002h
4C002003h
4C002004h
4C002005h
4C000008h
4C000009h
4C00000Fh
4C000010h
4C000011h
4C000012h
4C000013h
4C000014h
Address
Address
MSR
MSR
GeodeLink™ Control Processor Register Descriptions
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
Table 6-85. Standard GeodeLink™ Device MSRs Summary
Register Name
GLD Capabilities MSR (GLD_MSR_CAP)
GLD Master Configuration MSR
(GLD_MSR_CONFIG)
GLD SMI MSR (GLD_MSR_SMI)
GLD Error MSR (GLD_MSR_ERROR)
GLD Power Management MSR
(GLD_MSR_PM)
GLD Diagnostic MSR (GLD_MSR_DIAG)
Register Name
GLCP Clock Disable Delay Value
(GLCP_CLK_DIS_DELAY)
GLCP Clock Mask for Sleep Request
(GLCP_PMCLKDISABLE)
Chip Fabrication Information (GLCP_FAB)
GLCP Global Power Management Controls
(GLCP_GLB_PM)
GLCP Debug Output from Chip
(GLCP_DBGOUT)
GLCP Processor Status (GLCP_PROCSTAT)
GLCP DOWSER (GLCP_DOWSER)
GLCP I/O Delay Controls
(GLCP_DELAY_CONTROLS)
GLCP Clock Control (GLCP_CLKOFF)
GLCP Clock Active (GLCP_CLKACTIVE)
GLCP Clock Mask for Debug Clock Stop
Action (GLCP_CLKDISABLE)
GLCP Clock Active Mask for Suspend
Acknowledge (GLCP_CLK4ACK)
GLCP System Reset and PLL Control
(GLCP_SYS_RSTPLL)
Table 6-86. GLCP Specific MSRs Summary
tables that include reset values and page references where
the bit descriptions are provided.
Note: The MSR address is derived from the perspective
of the CPU Core. See Section 4.1 "MSR Set" on
page 45 for more details on MSR addressing.
00000000_00000001h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000 00000000h
Bootstrap Dependant
00000000_00002400h
00000000_0000001Fh
00000000_00000000h
00000000_00000000h
00000000_00000015h
00000000_00000000h
Bootstrap specific
Input Determined
Reset Value
Reset Value
33234C
Reference
Reference
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