ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 35

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Signal Definitions
3.4.3
AMD Geode™ LX Processors Data Book
Signal Name
CS[3:0]#
RAS[1:0]#
CAS[1:0]#
WE[1:0]#
BA[1:0]
MA[13:0]
TLA[1:0]
DQS[7:0]
DQM[7:0]
Memory Interface Signals (DDR) (Continued)
page 30
Table 3-
C6, H3,
A6, G2,
D30,
D27,
C20,
N31,
C19,
N30,
H29,
C24,
F29,
F28,
E29,
A28,
B13,
B23,
A10,
A19,
B10,
6 on
J29,
Ball
B28
C26
E28
C27
D26
See
B15
No.
M2
M1
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
up to 200 Mb/s
up to 200 Mb/s
up to 200 Mb/s
up to 200 Mb/s
up to 200 Mb/s
up to 200 Mb/s
up to 200 Mb/s
up to 200 MHz
166-400 Mb/s
f
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
V
Description
Chip Selects. The chip selects are used to select
the module bank within the system memory. Each
chip select corresponds to a specific module
bank.
If CS# is high, the bank(s) do not respond to
RAS#, CAS#, or WE# until the bank is selected
again.
Row Address Strobe. RAS#, CAS#, WE#, and
CKE are encoded to support the different SDRAM
commands. RAS0# is used with CS0# and CS1#.
RAS1# is used with CS2# and CS3#.
Column Address Strobe. RAS#, CAS#, WE#,
and CKE are encoded to support the different
SDRAM commands. CAS0# is used with CS0#
and CS1#. CAS1# is used with CS2# and CS3#.
Write Enable. RAS#, CAS#, WE#, and CKE are
encoded to support the different SDRAM com-
mands. WE0# is used with CS0# and CS1#.
WE1# is used with CS2# and CS3#.
Bank Address Bits. These bits are used to select
the component bank within the SDRAM.
Memory Address Bus. The multiplexed row/col-
umn address lines driven to the system memory.
Supports 256-Mbit SDRAM.
Memory Debug Pins. These pins provide useful
memory interface debug timing signals. (Should
be wired to DIMM slot.)
TLA[0] is wired to DQS[8] on the DIMM
TLA[1] is wired to CB[0] on the DIMM
DDR Data Strobe.
Data Mask Control Bits. During memory read
cycles, these outputs control whether the SDRAM
output buffers are driven on the Memory Data Bus
or not. All DQM signals are asserted during read
cycles.
During memory write cycles, these outputs control
whether or not memory data is written into the
SDRAM.
DQM[0] is associated with MD[7:0].
DQM[7] is associated with MD[63:56].
33234C
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