ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 273

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Graphics Processor Register Definitions
6.4.2.23 Width/Height (GP_CH3_WIDHI)
GP Memory Offset 68h
Type
Reset Value
This register is used to specify the width and the height of the bitmap to be fetched on channel 3 in pixels. This need not
match the destination width and height, as in the case of a rotation BLT where the width and height are swapped, but the
total number of pixels should be equal to the number of pixels in the destination.
6.4.2.24 Host Source (GP_CH3_HSRC)
GP Memory Offset 6Ch
Type
Reset Value
This register is used by software to load channel 3 data when the channel 3 pattern mode bit is not set, the channel 3
enable bit is set, and the channel 3 host source bit is set.This register is also aliased to the address range 400h-FFFh
allowing the processor to load large blocks of data to the GP using the repeat MOVS instruction.
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31
31:28
27:16
15:12
11:0
31:0
Bit
Bit
RSVD
30
29
28
Name
RSVD
WID
RSVD
HI
Name
HST_SRC
27
R/W
00000000h
WO
xxxxxxxxh
26
25
24
23
Description
Reserved. Write as read.
Width. Width in pixels of the BLT operation.
Reserved. Write as read.
Height. Height in pixels of the BLT operation.
Description
Host Source Data. Used during BLT in host source mode
22
WID
21
GP_CH3_WIDHI Bit Descriptions
GP_CH3_HSRC Bit Descriptions
20
GP_CH3_WIDHI Register Map
GP_CH3_HSRC Register Map
19
18
17
HST_SRC
16
15
RSVD
14
13
12
11
10
9
9
8
8
33234C
7
7
6
6
HI
5
5
4
4
3
3
2
2
1
1
273
0
0