ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 64

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

64
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:16
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
RSVD
AERR_MASK7
AERR_MASK6
AERR_MASK5
AERR_MASK4
AERR_MASK3
AERR_MASK2
AERR_MASK1
AERR_MASK0
AERR_FLAG7
(RO)
AERR_FLAG6
(RO)
AERR_FLAG5
(RO)
AERR_FLAG4
(RO)
AERR_FLAG3
(RO)
AERR_FLAG2
(RO)
AERR_FLAG1
(RO)
AERR_FLAG0
(RO)
33234C
RSVD
Description
Reserved.
Asynchronous Error Mask for Port 7 (GLIU0: Not Used; GLIU1: Not Used). Write 0 to
allow Port 7 to generate an AERR. AERR status is reported in bit 7.
Asynchronous Error Mask for Port 6 (GLIU0: Not Used; GLIU1: SB (Security
Block)). Write 0 to allow Port 6 to generate an AERR. AERR status is reported in bit 6.
Asynchronous Error Mask for Port 5 (GLIU0: GP; GLIU1: VIP). Write 0 to allow Port 5
to generate an AERR. AERR status is reported in bit 5.
Asynchronous Error Mask for Port 4 (GLIU0: DC; GLIU1: GLPCI). Write 0 to allow
Port 4 to generate an AERR. AERR status is reported in bit 4.
Asynchronous Error Mask for Port 3 (GLIU0: CPU Core; GLIU1: GLCP). Write 0 to
allow Port 3 to generate an AERR. AERR status is reported in bit 3.
Asynchronous Error Mask for Port 2 (GLIU0: Interface to GLIU1; GLIU1: VP). Write
0 to allow Port 2 to generate an AERR. AERR status is reported in bit 2.
Asynchronous Error Mask for Port 1 (GLIU0: GLMC; GLIU1: Interface to GLIU0).
Write 0 to allow Port 1 to generate an AERR. AERR status is reported in bit 1.
Asynchronous Error Mask for Port 0 (GLIU0: GLIU; GLIU1: GLIU). Write 0 to allow
Port 0 to generate an AERR. AERR status is reported in bit 0.
Asynchronous Error for Port 7 (GLIU0: Not Used; GLIU1: Not Used) (Read Only). If
1, indicates that an AERR was generated by Port 7. Cleared by source.
Asynchronous Error for Port 6 (GLIU0: Not Used; GLIU1: SB (Security Block))
(Read Only). If 1, indicates that an AERR was generated by Port 6. Cleared by source.
Asynchronous Error for Port 5 (GLIU0: GP; GLIU1: VIP) (Read Only). If 1, indicates
that an AERR was generated by Port 5. Cleared by source.
Asynchronous Error for Port 4 (GLIU0: DC; GLIU1: GLPCI) (Read Only). If 1, indi-
cates that an AERR was generated by Port 4. Cleared by source.
Asynchronous Error for Port 3 (GLIU0: CPU Core; GLIU1: GLCP) (Read Only). If 1,
indicates that an AERR was generated by Port 3. Cleared by source.
Asynchronous Error for Port 2 (GLIU0: Interface to GLIU1; GLIU1: VP) (Read Only).
If 1, indicates that an AERR was generated by Port 2. Cleared by source.
Asynchronous Error for Port 1 (GLIU0: GLMC; GLIU1: Interface to GLIU0) (Read
Only). If 1, indicates that an AERR was generated by Port 1. Cleared by source.
Asynchronous Error for Port 0 (GLIU0: GLIU; GLIU1: GLIU) (Read Only). If 1, indi-
cates that an AERR was generated by Port 0. Cleared by source.
AERR Bit Descriptions
AERR Register Map
RSVD
AMD Geode™ LX Processors Data Book
9
8
7
GLIU Register Descriptions
6
5
4
3
2
1
0